JPS5487052A - Digital circuit - Google Patents

Digital circuit

Info

Publication number
JPS5487052A
JPS5487052A JP15467477A JP15467477A JPS5487052A JP S5487052 A JPS5487052 A JP S5487052A JP 15467477 A JP15467477 A JP 15467477A JP 15467477 A JP15467477 A JP 15467477A JP S5487052 A JPS5487052 A JP S5487052A
Authority
JP
Japan
Prior art keywords
circuit
output
clock signal
flop
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15467477A
Other languages
Japanese (ja)
Inventor
Yasuo Kusumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP15467477A priority Critical patent/JPS5487052A/en
Publication of JPS5487052A publication Critical patent/JPS5487052A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence

Abstract

PURPOSE:To insure the normal operation for the overall device for the clock signal source circuit of the digital circuit by obtaining the signal source of the lowest frequency among plural units of the clock signal sources. CONSTITUTION:Oscillation frequency f1 and f1' generated from oscillator circuit 1 and 1' independent to each other are supplied to divider circuit 2 and 2' and then to flip-flop 5 via flip-flop 3 and 3' memorizing the output plus AND circuit 4. The output CL turns to the clock signal. Then the output of the full step number of circuit 2 and 2' plus the output of circuit 4 are supplied to circuit 4.
JP15467477A 1977-12-22 1977-12-22 Digital circuit Pending JPS5487052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15467477A JPS5487052A (en) 1977-12-22 1977-12-22 Digital circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15467477A JPS5487052A (en) 1977-12-22 1977-12-22 Digital circuit

Publications (1)

Publication Number Publication Date
JPS5487052A true JPS5487052A (en) 1979-07-11

Family

ID=15589415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15467477A Pending JPS5487052A (en) 1977-12-22 1977-12-22 Digital circuit

Country Status (1)

Country Link
JP (1) JPS5487052A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128253U (en) * 1981-02-05 1982-08-10

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128253U (en) * 1981-02-05 1982-08-10

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