JPS6412719A - Initial value setting circuit - Google Patents

Initial value setting circuit

Info

Publication number
JPS6412719A
JPS6412719A JP16902287A JP16902287A JPS6412719A JP S6412719 A JPS6412719 A JP S6412719A JP 16902287 A JP16902287 A JP 16902287A JP 16902287 A JP16902287 A JP 16902287A JP S6412719 A JPS6412719 A JP S6412719A
Authority
JP
Japan
Prior art keywords
initial value
output terminal
value setting
setting circuit
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16902287A
Other languages
Japanese (ja)
Inventor
Masao Ikushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16902287A priority Critical patent/JPS6412719A/en
Publication of JPS6412719A publication Critical patent/JPS6412719A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To surely output an initial value even when a source voltage drops in a moment due to momentary power failure, etc., by connecting a P-channel MOS transistor whose gate is connected to a power source line to a capacitor in parallel. CONSTITUTION:The source of the P-channel MOS transistor is connected to the output terminal of an initial value setting circuit, and its gate to the power source line, and its drain to the ground, and the output terminal 4 is connected to the input terminal of an inverter 5. When the source voltage drops in a moment due to the momentary power failure, etc., the P-channel MOS transistor 9 is energized, and electric charge accumulated in the capacitor 3 is discharged, then, the level of the output terminal of the initial value setting circuit goes to a low level. Next, when the source voltage begins to increase again, the P-channel MOS transistor 9 is cut off, thereby, the level of the output terminal of the initial value setting circuit goes to the low level, and it is possible to set the level of the output terminal 8 in an OR circuit 6 at a high level uniquely.
JP16902287A 1987-07-07 1987-07-07 Initial value setting circuit Pending JPS6412719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16902287A JPS6412719A (en) 1987-07-07 1987-07-07 Initial value setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16902287A JPS6412719A (en) 1987-07-07 1987-07-07 Initial value setting circuit

Publications (1)

Publication Number Publication Date
JPS6412719A true JPS6412719A (en) 1989-01-17

Family

ID=15878873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16902287A Pending JPS6412719A (en) 1987-07-07 1987-07-07 Initial value setting circuit

Country Status (1)

Country Link
JP (1) JPS6412719A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005091503A1 (en) * 2004-03-19 2005-09-29 Renesas Technology Corp. Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005091503A1 (en) * 2004-03-19 2005-09-29 Renesas Technology Corp. Semiconductor integrated circuit device

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