JPS6411543U - - Google Patents
Info
- Publication number
- JPS6411543U JPS6411543U JP10521287U JP10521287U JPS6411543U JP S6411543 U JPS6411543 U JP S6411543U JP 10521287 U JP10521287 U JP 10521287U JP 10521287 U JP10521287 U JP 10521287U JP S6411543 U JPS6411543 U JP S6411543U
- Authority
- JP
- Japan
- Prior art keywords
- storage carrier
- semiconductor wafer
- wafer storage
- grooves
- semiconductor wafers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 235000012431 wafers Nutrition 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Packaging Frangible Articles (AREA)
- Warehouses Or Storage Devices (AREA)
- Sheets, Magazines, And Separation Thereof (AREA)
- Weting (AREA)
Description
第１図は本考案の実施例を示す半導体ウエハ収
納キヤリアの概略平面図、第２図はその半導体ウ
エハ収納キヤリアの正面図、第３図は本考案の他
の実施例を示す半導体ウエハ収納キヤリアの要部
平面図、第４図は従来の半導体ウエハ収納キヤリ
アの概略平面図、第５図はその半導体ウエハ収納
キヤリアの正面図、第６図は従来の半導体ウエハ
収納キヤリアの問題点を説明する図である。
５…ウエハ、１０，２０…ウエハ収納キヤリア
、１１，２１…側板、１２，２２…溝、１３，１
３ｂ，２３ａ…端辺部。
Fig. 1 is a schematic plan view of a semiconductor wafer storage carrier showing an embodiment of the present invention, Fig. 2 is a front view of the semiconductor wafer storage carrier, and Fig. 3 is a semiconductor wafer storage carrier showing another embodiment of the invention. 4 is a schematic plan view of a conventional semiconductor wafer storage carrier, FIG. 5 is a front view of the semiconductor wafer storage carrier, and FIG. 6 explains problems with the conventional semiconductor wafer storage carrier. It is a diagram. 5...Wafer, 10,20...Wafer storage carrier, 11,21...Side plate, 12,22...Groove, 13,1
3b, 23a...edge portions.
Claims (1)
隔に半導体ウエハの端部が係合可能な複数の溝を
縦方向に設けてなる半導体ウエハの収納キヤリア
において、 前記対向する溝の幅方向の深さを一列毎に、又
は複数単位列の溝毎に交互に異なるように設ける
ようにしたことを特徴とする半導体ウエハ収納キ
ヤリア。[Claims for Utility Model Registration] In a storage carrier for semiconductor wafers, the semiconductor wafer storage carrier is provided with a plurality of grooves vertically arranged at equal intervals on the inner wall surfaces of a pair of opposing side plates and into which the ends of the semiconductor wafers can be engaged. 1. A semiconductor wafer storage carrier characterized in that the depth of the grooves in the width direction is provided to be different for each row or for each groove of a plurality of unit rows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10521287U JPS6411543U (en) | 1987-07-10 | 1987-07-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10521287U JPS6411543U (en) | 1987-07-10 | 1987-07-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6411543U true JPS6411543U (en) | 1989-01-20 |
Family
ID=31337619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10521287U Pending JPS6411543U (en) | 1987-07-10 | 1987-07-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6411543U (en) |
-
1987
- 1987-07-10 JP JP10521287U patent/JPS6411543U/ja active Pending