JPS6410726A - Bus potential hold circuit - Google Patents

Bus potential hold circuit

Info

Publication number
JPS6410726A
JPS6410726A JP62163895A JP16389587A JPS6410726A JP S6410726 A JPS6410726 A JP S6410726A JP 62163895 A JP62163895 A JP 62163895A JP 16389587 A JP16389587 A JP 16389587A JP S6410726 A JPS6410726 A JP S6410726A
Authority
JP
Japan
Prior art keywords
bus
circuit
output
switch part
hold circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62163895A
Other languages
Japanese (ja)
Inventor
Kazuhiro Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62163895A priority Critical patent/JPS6410726A/en
Publication of JPS6410726A publication Critical patent/JPS6410726A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent the increase of power consumption by providing an OR circuit, which inputs all control signals in parallel, and a switch part, which turns on or off according to the output of the OR circuit. CONSTITUTION:All the control signals Ca,Cb, ...Cn, which control the output terminals of drivers 1a, 1b, ...1n, connected to a bus 3, so as to be turned into a high impedance state respectively, are inputted to the OR circuit 4, and the switch part 6 which is controlled by the output of the OR circuit 4, and connects between the power source 5 of a prescribed potential and the bus 3, is provided. When the bus 3 comes to the high impedance state, the output of the OR circuit 4 controls immediately the switch part 6, and connects between the bus 3 and the power source 5 of the prescribed potential. Thus, even when the bus 3 is enable, such a situation that L level can not be maintained, or a large current flows so that the power consumption increases, never takes place.
JP62163895A 1987-07-02 1987-07-02 Bus potential hold circuit Pending JPS6410726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62163895A JPS6410726A (en) 1987-07-02 1987-07-02 Bus potential hold circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62163895A JPS6410726A (en) 1987-07-02 1987-07-02 Bus potential hold circuit

Publications (1)

Publication Number Publication Date
JPS6410726A true JPS6410726A (en) 1989-01-13

Family

ID=15782849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62163895A Pending JPS6410726A (en) 1987-07-02 1987-07-02 Bus potential hold circuit

Country Status (1)

Country Link
JP (1) JPS6410726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281299A (en) * 1991-07-05 1994-01-25 Institut Max Von Laue Method for manufacturing a crystal with a lattice parameter gradient

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281299A (en) * 1991-07-05 1994-01-25 Institut Max Von Laue Method for manufacturing a crystal with a lattice parameter gradient

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