JPS639964A - Manufacture of semiconductor storage element - Google Patents

Abstract

PURPOSE:To avoid the generation of a crystal defect often viewed after forming an element by selecting the direction of the sidewall of a capacitance groove and the direction of the pattern of the element in the direction equivalent to <100>. CONSTITUTION:The boundaries of element regions 1 and field oxide regions 3 for isolating the element regions 1 and the direction of the boundaries, the direction of the patterns of the elements, are selected in the direction equivalent to <100>. The directions vertical to the sidewall surfaces of capacitance grooves 2 are also directed in the direction equivalent to <100>. A wafer in which a P-type silicon layer 4 having 2mum thickness and 10OMEGA.cm resistivity is shaped onto a boron-doped (100)P++ type silicon substrate 5 having 0.005OMEGA.cm resistivity and an orientation flat in the direction equivalent to <100> is prepared, thus forming a desired storage element. Accordingly, no crystal defect is generated on the interface of the P-type silicon layer 4 and the P++ type silicon substrate 5, thus also lengthening the memory holding time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor memory element, and particularly to a method for manufacturing a semiconductor memory element using an insulated gate field effect transistor.

[Conventional technology]

BACKGROUND ART The increase in capacity and density of semiconductor memory devices mounted on silicon semiconductor substrates is rapidly progressing with the development of new circuit configurations and microfabrication technology for mounting semiconductor substrates. Under these circumstances, the information storage department is currently limited to one MO
The next semiconductor memory element, which is composed of an S transistor and one information storage capacitor, is considered to be the most suitable for high density storage.
A method has been adopted in which the information storage capacitor is formed on the side wall of a groove several microns deep on the surface of a silicon substrate to increase the density.

Figure 2 and Figure 4 show an example of this.

FIG. 4 is a plan view of the (100) substrate after manufacturing the memory element.
Element area l, capacitance 1!12 e 74-Led awakening area 3
I'll show you only. As shown in FIG. 4, the memory element is
It is formed in a device region 1 having pattern edges in the (011) and (011> directions.The information storage capacitor portion is formed on the side wall portion of the capacitance trench 2.The device region 1 is separated from the field oxidation region 3. BB' in Figure 4.
An example of the device structure in cross section is shown in FIG. In FIG. 2, information charges are accumulated inside the dielectric film 7 formed on the sidewalls of the trench. Polysilicon a8 inside dielectric film 7
contains, for example, an N-type impurity and serves as a capacitive electrode.

This polysilicon film 8 is electrically connected to the source and contact regions 9 of the Mado, and is connected to the drain region lO
, gate oxide film 11, gate electrode 12. Information 1 is input/output to/from the MOS transistor consisting of the source region 9.

Such a memory element is described, for example, in the academic journal International Electron Technology Meeting Technical Digest, 1985, page 710 (IE
L)M, 'l'ech, i)ig, , 1985
．． Pp-710-713).

[Problems to be Solved by the Invention] When manufacturing a device having the unique device structure shown in FIG. 2, crystal defects are likely to occur near the interface between the P-type silicon substrate and the R-type silicon substrate 5, and Another drawback is that information charges tend to leak from the contact region 9 toward the r-type silicon substrate 5. In the memory element shown in FIG. 2, the P+' type silicon substrate 5 serves as a counter electrode of the information storage capacitor section, and is desired to have as low a resistance as possible. However, when the resistance is lowered, that is, when impurities are added at a high concentration, the lattice constant of the P type silicon substrate 5 deviates from the original lattice constant of silicon. When a P-type silicon layer is epitaxially grown on a P-type silicon substrate, crystal defects occur at the interface between the P-type silicon layer 4 and the P-type silicon substrate 5. Therefore, an impurity concentration is usually selected that does not cause crystal defects even during epitaxial growth. However, as semiconductor memory devices become more highly integrated, the device structure becomes more complex, such as the one shown in Figure 2.
Numerous processes must be completed before a device is completed. This rule applies even if no crystal defects occur before the device structure process.

Crystal defects are likely to be introduced after the device manufacturing process.

The occurrence of such crystal defects is not limited to only P-type silicon substrates having a P-type silicon layer on the surface;
The same applies to the case where an N-type silicon epitaxial film is formed on a silicon substrate doped with 0 atoms/byte of anti-sb. For this reason, even if a semiconductor memory element as shown in Fig. 2 is formed using a wafer having a silicon layer on its surface with an impurity concentration significantly different from that of the substrate, no crystal defects will occur. A device manufacturing method is required.

[Means for solving problems]

In the present invention, in order to suppress the occurrence of crystal defects even after the device manufacturing process has been completed, the direction of the 9111 wall of the capacitive groove and the pattern direction of the device are set to (100) instead of the conventional direction equivalent to <110>. Choose an equivalent direction.

In the method for manufacturing a semiconductor memory element of the present invention, an information storage capacitor section is formed in a low concentration silicon layer and a high a degree silicon substrate having the same conductivity type as this low 11 degree silicon layer, and an insulated gate field effect transistor of an information transmission section is formed. In a method for manufacturing a semiconductor memory element in which a semiconductor memory element whose source region is electrically connected to the information storage capacity part is formed on a silicon substrate having a (Zoo) or (110) plane orientation, the information storage capacity part is electrically connected to the information storage capacity part. The vertical direction of the l++ wall surface of the groove and the pattern edge direction of the field oxide film for separating the device region consisting of the information storage capacitor section and the information transmission section from each other are examined 100>
0 [Example] Next, the present invention will be described with reference to the drawings.

1 to 3 are for explaining a first embodiment of the present invention. Figure 1 is a plan view of the board.

The boundary of the device region 1 and the field oxidation region 3 for separating the device regions, that is, the pattern direction of the device is (1
00> is selected in the direction equivalent to 00>.

Again, Yong! l: The direction perpendicular to the side wall surface of the groove 2 is also a direction equivalent to (100). The substrate plane orientation is (100). Note that in the figure, element region 1. t442. Only field oxide region 3 is shown. FIG. 2 corresponds to a part of the cross-sectional structure at 8 in FIG. 1.

FIG. 3 is a longitudinal sectional view showing the manufacturing process of the element shown in FIG. 2. It has an orientation flat in a direction equivalent to (100). boron dope.

A P-type silicon layer 4 with a thickness of 2 μm and a resistivity of 10Ω·α is formed on a (100) P-type silicon substrate 5 with a resistivity of 0.005Ω·α, and a t-wafer is prepared (see FIG. 3(a).
)). Next, a capacitive groove 15 and an element isolation region (field oxidation region) 6 are formed using a conventional reactive ion etching technique and a selective etching technique, as shown in FIG. 3(b). Next, as shown in FIG. 3C, a dielectric film made of a thin oxide film of about 200 Å thick is formed on the sidewalls of the capacitance trench 15 to cover the P-type silicon layer 4 and the surface of the element isolation region 60. 7. Here, the dielectric film of the contact portion 16 is removed using a normal etching technique.Next, as shown in FIG. 3(d), an N-type impurity, For example, a polysilicon film 8 containing phosphorus at 1×10 atoms/crIL is formed.The N-type impurity contained in the polysilicon film 8 in this step diffuses into the contact region 16, and a dovetail-P junction is formed in this region. Thereafter, the surface of the polysilicon film 8 is thermally oxidized to form an insulating oxide film 17. Next, as shown in FIG.
1. After forming the gate electrode 12, an N-type impurity 6, for example, phosphorus atoms, is introduced into the surface of the P-type silicon layer 4 by ion implantation, and then the drain region 10. A source region 9 is formed to be electrically connected to the contact region, and an interlayer insulating film 13 and electrode wiring 14 are formed to drain the liquid, thereby forming a desired memory element.

A large number of memory elements are formed using this process.As a result of examining the wafer using X-ray topography, no co-crystalline defects were observed at the interface between the P-type silicon layer 4 and the P-type silicon substrate 5. , the memory retention time is 5 to 10 times longer than when manufactured using conventional methods.

Next, a second embodiment of the present invention will be described.

In this example, (110) was used as the substrate surface orientation. (
100) has an orientation flat in a direction equivalent to 100). Specific resistance 0.0050・α, boron-doped P
A P-type silicon substrate was prepared, and a P-type silicon layer with a thickness of 2 μm and a specific resistance of 10 Ω·a was epitaxially grown on the P-type silicon substrate. Using such a substrate, a memory element having the same structure as shown in FIG.
It was formed so that the direction is equivalent to that of the The device manufacturing process used exactly the same method as described in the first example. As a result, as in the case of the (100) substrate shown in the first example, no crystal defects were observed near the interface between the P-type silicon layer and the P-type silicon substrate.

By setting the direction of the side wall of the capacitor groove and the direction of the element pattern to be equivalent to (10), a memory retention time that is 5 times 8 times longer than that of the conventional method can be obtained.

〔Effect of the invention〕

In the above-described method, the present invention does not include a silicon layer on the surface of which the impurity content is significantly different from that of the substrate.
When manufacturing memory elements on 100) or (110) wafers, the capacitive groove sidewall direction and the element pattern direction are set to (1
By selecting a direction equivalent to (00), it is possible to completely avoid generation of friend crystal defects, which are often found after device manufacturing, compared to the conventional method of making these directions equivalent to (110).

As a result, leakage of information charges can be reduced, and a memory retention time that is 5 to 10 times longer than that of the conventional method can be obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view of the substrate after forming a memory element in the first embodiment of the present invention, and FIG. 2 is a cross section taken along the line 8-- in FIG. 1 and taken along the line B-B' in FIG. 4. 3 is a process sectional view showing the manufacturing process of the device shown in FIG. 2, and FIG. 4 is a plan view of the substrate when the device is formed by a conventional method. DESCRIPTION OF SYMBOLS 1... Element region, 2, 15... Capacitive trench, 3... Field oxidation region, 4... P-type silicon layer, 5...
P type silicon substrate, 6... element isolation region, 7...
dielectric film, 8... polysilicon layer, 9... source and contact region, 10... drain region, 11...
...Gate oxide film, 12...Gate electrode, 13...
Interlayer insulating film, 14... Electrode wiring, 16... Contact portion, 17... Insulating oxide film. Agent Patent Attorney Uchihara XIJL ,','
−,' : を日 ``・． （。 ku, -12, ′ Tumulus Chii drawing ko concave

Claims (1)

[Claims] An information storage capacitor section is formed in a groove of a low concentration silicon layer and a high concentration silicon substrate having the same conductivity type as the low concentration silicon layer, and a source region of an insulated gate field effect transistor of the information transmission section is connected to the information storage capacitor section. In a method for manufacturing a semiconductor memory element in which an electrically connected semiconductor memory element is formed on a silicon substrate having a (100) or (110) plane orientation, the vertical direction of the side wall surface of the groove of the information storage capacitor section, and A method for manufacturing a semiconductor memory device, characterized in that a pattern edge direction of a field oxide film for separating the device region consisting of the information storage capacitor section and the information transmission section from each other is set in a direction equivalent to <100>.