JPS6398071A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To make the scaling of an input sample and a comparison pattern unnecessary, and to compress a circuit scale required for distance calculation, by providing the number of arithmetic bits of an accumulator on a high-order side more than the output of a distance calculation circuit. CONSTITUTION:The input samples x0, x1,...x127 from a terminal 1, and the comparison patterns s0, s1,...s127 from a terminal 2, are inputted simultaneously. A value at this time is set at the value from -1 to 1 in the complementary expression of 2 of 8 bits. After the delay of the time of the distance calculation from those inputs, the outputs ¦x0-s0¦, ¦x1-s1¦,...¦x127-s127¦ can be obtained in order from the distance calculation circuit 3. At the accumulator 4, the outputs of 128 from the circuit 3 are accumulated. At this time, since the accumulator 4 has the number of bits possible to hold values of 128 times the output of the circuit 3, numerals from 0 to 256 can be handled. Thereby, accumulation without generating overflow can be performed in the accumulator 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic circuit, and particularly to an arithmetic circuit for a digital signal processor.

[Conventional technology]

Vector quantization is attracting attention in digital signal processing. In this vector quantization, an operation often used is distance calculation between two input vectors. Conventionally, there are general-purpose signal processing processors that can perform product-sum operations at high speed. - For example, NEC Corporation's μPD772
0, and a detailed explanation can be found in μP D published in January 1986.
7720 Family Signal Processor User's
I'll leave it to the manual, but when it comes to calculation blocks, 1.
There is a 6-bit parallel multiplier and a 16-bit arithmetic and logic circuit, and a so-called sum-of-products operation, which accumulates the multiplier outputs, can be executed every instruction cycle.

[Problem that the invention seeks to solve]

However, the μP D7720 has only one arithmetic and logic operation circuit, and requires a large number of steps to calculate the absolute value of the difference, which is one distance measure.For example, the 128-dimensional vector shown in equation (1) requires a large number of steps. When calculating the distance of Input sample x(i): 1≦x(i)<1 Comparison pattern 5(i): L≦5(i)<1, the dynamic range after accumulation is O〈 D<256. Therefore, in order to prevent overflow in an arithmetic circuit that can only express numerical values from -1 to 1 or from O to 2, it is necessary to scale the input samples and comparison patterns.

To explain this scaling in more detail, it means rewriting equation (1) shown above into equation (2).

Input sample x(i) knee 1/128≦x(i)/128<1/128
Comparison pattern 5 (i) By setting knee 1/128≦s (i)/12B < 1/12B, the dynamic range after accumulation is O<
D<2.

An object of the present invention is to provide an arithmetic circuit that can directly calculate a distance calculation formula with one instruction per sample without requiring scaling.

[Means for solving problems]

The arithmetic circuit of the present invention includes a two-input distance calculation circuit, an accumulator connected to the output of the distance calculation circuit, and an accumulator connected to the output of the accumulator, and shifts to the right by an arbitrary number of bits. It comprises a barrel shifter and a register that supplies the number of bits to be shifted to the barrel shifter, and the number of operation bits of the accumulator is higher than the output of the distance calculation circuit, and the operation can be performed without overflowing. It is characterized by

[Effect]

According to the invention, it is assumed that the input sample and the comparison pattern each take a value between -1 and 1. That is, if the absolute value of the difference is used as the distance measure, the output will be between 0 and 2. Since N distance calculation circuits are used for accumulation, the dynamic range is expanded from 0 to 2N.

Therefore, in the accumulator according to the present invention, a plurality of bits for preventing overflow are present above the MSB of the distance calculation circuit output. This eliminates the need to scale input samples and comparison patterns, and reduces the circuit scale for distance calculations. At this time, for example, the distance defined by equation (1) needs to be divided by the cumulative number N mentioned above so that it becomes a value between 0 and 2. However, in general signal processing, the cumulative number N is often a power of 2, and the division can be replaced by a right shift operation instead of the division.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
This arithmetic circuit includes a distance calculation circuit 3, an accumulator 4, a barrel shifter 5, and a register 6 that supplies a shift amount to the barrel shifter 5.

Note that 1.2 is an input terminal of the distance calculation circuit.

The distance calculation circuit 3 calculates the absolute value of the difference, each input is an 8-bit two's complement representation, and the output is an 8-bit natural two's complement representation.
It becomes a base number. Details of this distance calculation circuit 3 will be described later. While the output of the distance calculation circuit 3 is 8 bits, the accumulator 4 has a precision of 16 bits. Details of the accumulator 4 will also be described later. Further, the barrel shifter 5 outputs consecutive 8 bits from an arbitrary position specified by the 3-bit register 6 among the 16 bits input. This barrel shifter 5 can be realized by using a plurality of Am25S10 manufactured by AMD. Details of the Am25S10 are described in the Bipolar Microprocessor Logic and Interface 1985 Data Book published by AMD.

When calculating equation (1) using the arithmetic circuit shown in FIG. 1, as an initial state, the value held in the accumulator 4 is “
0", and shift i "7" is set in register 6 to perform a shift of 1/128. Input samples x(0), x(1)...x are input from input terminal 1. (
127) from input terminal 2 to comparison pattern s (0)
, s (1) ...5 (127) are input simultaneously. Each value at this time takes a value from -1 to 1 in 8-bit two's complement representation. After a delay of the distance calculation time from these inputs, the distance calculation circuit 3 outputs 1x(0)-s (0)l, lx (1)-s (1)
l...l x (127) -s (127) l
The output of is obtained sequentially.

These outputs are all values between 0 and 2 and can be expressed as 8-bit natural binary numbers. The accumulator 4 accumulates 128 outputs from the distance calculation circuit 3.

At this time, as mentioned earlier, the accumulator 4 is connected to the distance calculation circuit 3.
Since the number of bits is such that it can hold a value 128 times larger than the output of , it can handle numbers from 0 to 256. From this, the accumulator 4 can perform accumulation without overflowing. After 128 accumulations, the barrel shifter 5 executes 1/128. barrel shifter 5
A control signal indicating that the output is 1/128 is input from the register 6, and by selecting the upper 8 bits of the output of the accumulator 4, the 8 bits of the output of the barrel shifter 5 are set to 1/128. realizable.

FIG. 2 is a detailed diagram of the distance calculation circuit 3 of FIG. 1. The distance calculation circuit 3 is comprised of two subtracters 7.8 each having an 8-bit input and a 9-bit output in two's complement representation, and a selection circuit 9. Input terminal 1 is connected to the A input of subtractor 7 and the B input of subtractor 8. Similarly, input terminal 2 is
It is connected to the B input of the subtractor 7 and the A input of the subtractor 8. With this connection, the subtracter 7 calculates (input from input terminal 1) - (input from input terminal 2), and the subtracter 8 calculates (input from input terminal 2) - (input from input terminal 1). input) is calculated. The output of subtractors 7 and 8 is 2
It has a precision of 9 bits in complement representation, and no overflow occurs during subtraction.

Therefore, by looking at the MSB of the output of subtractor 7,
It can be seen whether the output of the subtracter 7 is positive or negative. Therefore, the selection circuit 9 whose selection is controlled by this MSB bit can select the positive side subtraction output.

FIG. 3 is a detailed explanatory diagram of the accumulator 4 of FIG. 1. This accumulator 4 is composed of a 16-bit adder 10 and a 16-bit register 11. The adder 10 extends the output 8 bits of the distance calculation circuit 3 shown in FIG. Then, the addition result is obtained as the output of the adder 10 and held in the register 11.

〔Effect of the invention〕

According to the present invention, distance calculation as shown in equation (1) can be realized without overflow by using an arithmetic circuit using a fixed-point arithmetic method. Furthermore, since there is no need to scale input samples and comparison patterns, the circuit scale required for distance calculation can be reduced.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the distance calculation circuit in FIG. 1, and FIG. 3 is a diagram showing the configuration of the distance calculation circuit in FIG. FIG. 3 is a diagram showing the configuration. 1.2... Input terminal 3 of distance calculation circuit...
...Distance calculation circuit 4 ...Accumulator 5 ...Barrel shifter 6 ...Register Fig. 2 Fig. 3

Claims (1)

[Claims] (1) a two-input distance calculation circuit; an accumulator connected to the output of the distance calculation circuit; a barrel shifter connected to the output of the accumulator and shifted to the right by an arbitrary number of bits; and a register for supplying the number of bits to be shifted to a barrel shifter, wherein the number of operation bits of the accumulator is higher than the output of the distance calculation circuit, and the operation can be performed without overflowing.