JPS6397868U - - Google Patents
Info
- Publication number
- JPS6397868U JPS6397868U JP19322586U JP19322586U JPS6397868U JP S6397868 U JPS6397868 U JP S6397868U JP 19322586 U JP19322586 U JP 19322586U JP 19322586 U JP19322586 U JP 19322586U JP S6397868 U JPS6397868 U JP S6397868U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- noise ratio
- pulse portion
- inter
- offset amount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Position Fixing By Use Of Radio Waves (AREA)
Description
第１図はクレーム対応図、第２図は従来装置の
作用を説明する波形図、第３図は本考案に係る装
置の全体構成説明図、第４図は第３図実施例の作
用を説明する信号波形図、第５図は第３図実施例
の作用を説明するフローチヤート、第６図は２値
化時基準レベルのオフセツト作用説明図である。
１０……アンテナ、１２……増幅器、１４……
２値化回路、１６……サンプリング回路、１８…
…ＣＰＵ、２０……ＲＡＭ、２２……ＳＮ比推定
データテーブル、２４……オフセツト補正データ
テーブル。
Fig. 1 is a diagram corresponding to claims, Fig. 2 is a waveform diagram explaining the operation of the conventional device, Fig. 3 is an explanatory diagram of the overall configuration of the device according to the present invention, and Fig. 4 is an illustration of the operation of the embodiment shown in Fig. 3. FIG. 5 is a flowchart for explaining the operation of the embodiment shown in FIG. 3, and FIG. 6 is a diagram for explaining the offset operation of the reference level during binarization. 10...Antenna, 12...Amplifier, 14...
Binarization circuit, 16...Sampling circuit, 18...
... CPU, 20 ... RAM, 22 ... SN ratio estimation data table, 24 ... offset correction data table.
Claims (1)
とパルス間部分とにおける所定の位相角で該信号
のレベルを極性判別して２値化データに変換する
入力信号２値化手段と、 両２値化データの個別カウントを所定回数行う
データ同期加算手段と、 パルス部分とパルス間部分とにおける信号雑音
比を両部分についての同期加算結果から各々推定
する信号雑音比推定手段と、 パルス性信号の極性判別基準となるレベルの仮
想オフセツト量に相当した値をパルス部分とパル
ス間部分とについて推定された信号雑音比により
求めるオフセツト量相当値演算手段と、 パルス部分についての信号雑音比を前記オフセ
ツト量の相当値とパルス間部分について推定され
た信号雑音比とにより求める信号雑音比演算手段
と、 を備えた、ことを特徴とする信号雑音比測定装置
。[Claims for Utility Model Registration] An input signal binary whose level is determined at a predetermined phase angle between a pulse portion and an inter-pulse portion of a pulsed signal having a constant pulse interval and converted into binary data. data synchronous addition means for individually counting both binary data a predetermined number of times; and signal-to-noise ratio estimating means for estimating the signal-to-noise ratio in the pulse portion and the inter-pulse portion from the synchronous addition results for both portions. and an offset amount equivalent value calculating means for calculating a value corresponding to a virtual offset amount of a level serving as a polarity determination standard of a pulsed signal using a signal-to-noise ratio estimated for a pulse portion and an inter-pulse portion, and a signal for the pulse portion. A signal-to-noise ratio measuring device comprising: signal-to-noise ratio calculation means for calculating a noise ratio from a value equivalent to the offset amount and a signal-to-noise ratio estimated for the inter-pulse portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19322586U JPS6397868U (en) | 1986-12-15 | 1986-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19322586U JPS6397868U (en) | 1986-12-15 | 1986-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6397868U true JPS6397868U (en) | 1988-06-24 |
Family
ID=31149050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19322586U Pending JPS6397868U (en) | 1986-12-15 | 1986-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6397868U (en) |
-
1986
- 1986-12-15 JP JP19322586U patent/JPS6397868U/ja active Pending
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