JPS639771B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a binary counter whose unit stage can be configured with a smaller number of gates than conventional ones.

As is well known, counters (including frequency dividers) that have been widely used in the past have a basic logic configuration of 6 NAND gates or 6 NOR gates.
A unit stage is constructed by an edge-trigger type T flip-flop circuit with interconnected gates.In recent years, this type of counter has become a central part of all digital systems, especially digital LSIs. Many attempts are being made to reduce the number of gates in the T flip-flop circuit that constitutes the unit stage of.

In particular, since I ² L ICs allow analog and digital circuits to be mixed together, their application to fields such as cameras, watches, and micromotor control circuits is remarkable.
The number of elements differs depending on whether the frequency is simply divided by a factor of 1 or when a reset function is added. ) was also announced, in which the unit stage was reduced to four elements.

These cases can be found in the IEEE JOURNAL OF
SOLID-STATE CIRCUITS, Vol.SC-11, No.
6 (1976) PP847-851 PATUCCI and LK
RUSSEL; “An I ² L Watch Chip With Direct
LED Drive” and the same IEEE magazine Vol.SC-14, No.3
(1979) PP657−660 U.ABLASSSMEIER;
“Camparison of Various Binary Dividers in
I ² L”.

However, these four-element flip-flop circuits cannot provide an inverted output as an output signal, or require a special structure different from conventional ones.

Furthermore, as shown in the latter paper, these four-element flip-flop circuits had a problem in that the usable limit frequency was significantly lowered due to their special configuration.

The present invention solves the above problems by providing a counter whose basic circuit has a unit stage constituted by five matching gates.

FIG. 1 is a logical configuration diagram of a 4-bit binary counter in an embodiment of the present invention _.
is the input terminal to which the clock signal is applied, terminal Q ₀ ,
Q ₁ , Q ₂ , Q ₃ are the 1st bit, 2nd bit, and
These are count output terminals for the 3rd and 4th bits.

In FIG. 1, NAND gates 11, 12, 13,
14, 15, and 16 constitute a first bit unit stage 100, and the unit stage 100 is a unit stage for supplying a trigger signal to a second bit unit stage 200 to which the present invention is applied. , it has the same function as a normal T flip-flop circuit with a differential pulse generation circuit added to the output side.

In the unit stage 200, each input terminal and output terminal are cross-coupled.
A first gate pair 201 is configured by a NAND gate 21 and a NAND gate 22, and a second gate pair 202 is configured by a similarly connected NAND gate 23 and a NAND gate 24.

Further, the output terminals of the NAND gates 21 and 22 are connected to the NAND gates 23 and 24, respectively.
Another input terminal of the NAND gates 21 and 22 are connected to each other, and the second input terminals of the NAND gates 21 and 22 are both NAND gates.
The third input terminal is connected to the output terminal of the gate 25, and the third input terminal is connected to the output terminal of the NAND gates 24 and 23, respectively.

Furthermore, the first input terminal 25a of the NAND gate 25 constitutes a unit stage 100.
Connected to the output terminal of the NAND gate 11, the second
The input terminal 25b of is connected to the output terminal of the NAND gate 21, and the fourth and fifth input terminals 22d and 22e of the NAND gate 22 are connected to the output terminals of the NAND gates 31 and 32 constituting the next unit stage 300, respectively. Connected to the terminal and said
The output terminal of the NAND gate 21 is connected to the next stage NAND.
A first input terminal of gate 35 is connected.

The unit stage 300 has NAND gates 31, 3
Unit stage 20 by 2, 33, 34, 35
0, the unit stage 400 is
It is constructed in the same manner as the unit stage 100 by NAND gates 41, 42, 43, 44, and 45.

Note that the unit stage 300 is composed of
The fourth and fifth input terminals of the NAND gate 32 are
each constitutes the unit stage 400.
Connected to the output terminals of NAND gates 41 and 42,
The output signal of the NAND gate 33 is supplied to the unit stage 400 as a trigger signal.

Now, since the circuit shown in FIG. 1 is particularly effective in reducing the number of elements when implemented in I ² L, we will summarize the operation based on the circuit connection diagram in which the unit stages 100 and 200 are configured with I ² L transistors. Explain.

First, FIG. 2 is a circuit connection diagram in which the logical configuration of the unit stage 100 in FIG. 1 is realized by an I ² L circuit.
In FIG. 2, the base of transistor 101 is connected to clock pulse input terminal ₀ , the first collector 1a is connected to the base of transistor 102, and the second collector 1b is connected to transistor 103.
The third collector 1c is connected to the base of the transistor 106. The first collector 2a of the transistor 102 is connected to the drive output terminal ₀ , and the second collector 2a of the transistor 102 is connected to the drive output terminal 0.
b is connected to the base of the transistor 103, the third collector 2c is connected to the base of the transistor 107, and the fourth collector 2d is connected to the base of the transistor 104. The first collector 3a of the transistor 103 is connected to the base of the transistor 102, the second collector 3b is connected to the base of the transistor 107, and the third collector 3c is connected to the base of the transistor 102.
It is connected to the base of 5.

Further, the first collector 4a of the transistor 104 is connected to the base of the transistor 105, and the second collector 4b is connected to the first bit output terminal.
The _third collector 4c is connected to the base of the transistor 103. The first collector 5a of the transistor 105 is connected to the base of the transistor 104, the second collector 5b is connected to the 1st bit inverted output terminal ₀ , and the third collector 5c is connected to the base of the transistor 102. ing.

Furthermore, the first collector 6a of the transistor 106 is connected to the base of the transistor 107, and the second collector 6b of the transistor 106 is connected to the base of the transistor 107.
The third collector 6c is connected to the base of the transistor 102. The first collector 7a of the transistor 107
is connected to the base of the transistor 106.

Now, Fig. 3 shows the signal waveforms of each part of the circuit of Fig. 2, and the second, third, and
The signal waveforms of the fourth collector are the first, second, and
It is assumed that the signal waveform of the third collector has a delay equivalent to one half of the signal transmission delay between gates. In Fig. 3, a indicates the clock pulse input to clock pulse input terminal ₀ , b~d, e~h, i~k, l~n, o~
q, rt and u are each transistor 10
1, the first to third collectors of the transistor 102, the first to fourth collectors of the transistor 103, and the first to fourth collectors of the transistor 103.
-Signal waveforms of the third collector, the first to third collectors of the transistor 104, the first to third collectors of the transistor 105, the first to third collectors of the transistor 106, and the first collector of the transistor 107 are shown. In an actual circuit, for example, the first collector 1a of the transistor 101 is commonly connected to the collectors 3a, 5c, and 6c of the transistors 103, 105, and 106.
A waveform different from the signal waveform shown in FIG. 3 appears, but in order to make the explanation of the operation easier to understand, FIG. 3 shows the respective collector waveforms when each collector is separated from the other collectors. In addition, A in Figure 2 is the delay time per gate,
B indicates the delay time per collector.

Now, the transistors 101, 104 in FIG.
When the output level of 107 is “0”, transistor 10
With the output levels of transistors 2, 103, 105, and 106 being "1", the level of the base of the transistor 101 at time _t1 is as shown in FIG.
As shown in , if the level of the first collector 1a of the transistor 101 shifts from "1" to "0", then the level of the first collector 1a of the transistor 101 shifts to "1", and then the level of the second collector 1a of the transistor 101 shifts to "1".
The levels of the collector 1b and the third collector 1c shift to "1" one after another.

When the level of the first collector 1a of the transistor 101 shifts to "1", the first collector 3a of the transistor 103, the third collector 5c of the transistor 105, and the transistor 106
Since the level of the third collector 6c of the transistor 102 is all "1", the level of the first collector 2a of the transistor 102 shifts to "0", and the level of the second collector 2b, the third collector 2c, and the transistor 102 shifts to "0". The fourth collector 2d shifts to "0" one after another.

When the level of the third collector 2c of the transistor 102 shifts to "0", the transistor 107
The output level of the first collector 7a of the transistor 101 shifts to "1", and at this point the level of the third collector 1c of the transistor 101 becomes "1".
The level of the first collector 6a of the transistor 106 shifts to "0", and the level of the second collector 6b,
The level of the third collector 6c shifts to "0" one after another.

When the level of the third collector 6c of the transistor 106 shifts to "0", the transistor 1
The level of the first collector 2a of 02 returns to "1", and the level of the second collector 2b, the third collector 2c,
The level of the fourth collector 2d also returns to "1" one after another.

On the other hand, at the time when the level of the fourth collector 2d of the transistor 102 shifts from "1" to "0" before returning to "1", the level of the first collector 4a of the transistor 104 shifts to "1", Subsequently, the levels of the second collector 4b and the third collector 4c also shift to "1".

When the level of the first collector 4a of the transistor 104 shifts to "1", since the level of the third collector 3c of the transistor 103 has already become "1", the level of the first collector 5a of the transistor 105 shifts to "0". ", and the levels of the second collector 5b and the third collector 5c successively shift to "0".

At time _t2 , when the level of the base of the transistor 101 shifts to "1", the level of the first collector 1a of the transistor 101 shifts to "0", followed by the level of the second collector 1b and the third collector. The level of 1c also shifts to "0" one after another.

When the level of the third collector 1c of the transistor 101 shifts to "0", the transistor 10
6 first collector 6a, second collector 6b, third collector
The level of collector 6c moves to "1" one after another,
By shifting the level of the first collector 6a of the transistor 106 to "1", the transistor 10
The level of the first collector 7a of clock pulse 7 shifts to "0" in preparation for the arrival of the leading edge of the clock pulse at time _t3 .

At time _t3 , when the level of the base of the transistor 101 shifts to "0", the level of the first to third collectors shifts to "1".

When the level of the second collector 1b of the transistor 101 shifts to "1", the second collector 2b of the transistor 102, the third collector 4c of the transistor 104, and the transistor 106
Since the level of the second collector 6b of the transistor 103 is "1", the level of the first collector 3a of the transistor 103 shifts to "0", and then the level of the second collector 3b and third collector 3c of the transistor 103 shifts to "0". The level also shifts to "0".

As the output level of the second collector 3b of the transistor 103 shifts to "0", the level of the first collector 7a of the transistor 107 shifts to "1", and on the other hand, the output level of the third collector 3c of the transistor 103 shifts to "1". As the level shifts to "0", the level of the first collector 5a of the transistor 105 shifts to "1".

When the level of the first collector 7a of the transistor 107 shifts to "1", the transistor 10
The level of the first collector 6a of the transistor 106 shifts to "0", and the level of the second collector 6b and third collector 6c of the transistor 106 also shifts to "0", and the level of the second collector 6b of the transistor 106 shifts to "0". Due to the transition to "0", the level of the first collector 3a of the transistor 103 returns to "1".

Note that during this time, the first
As the level of the collector 5a shifts to "1", the output level of the transistor 104 shifts to "0".

At time _t4 , when the level of the base of the transistor 101 shifts to "1", the output level of the transistor 101 shifts to "0", as at time _t2 , and as a result, the level of the base of the transistor 101 shifts to "0".
The output level of transistor 107 shifts to "1", and further the output level of transistor 107 shifts to "0".

Thereafter, in the same way, each time the level of the base of the transistor 101 changes, in other words, each time the level of the clock pulse input terminal ₀ changes, the output level of each transistor changes repeatedly.
When the level of the clock pulse input terminal ₀ of the circuit shown in FIG _{. 2} changes as shown in FIG.
The third bit is connected to the inverted output terminal ₀ .
Signal waveforms as shown in figures e, m, and p appear.

In other words, the circuit shown in FIG. 2 can be considered to be a circuit in which the function of a differential pulse generation circuit is added to an ordinary T flip-flop circuit.

Now, FIG. 4 is a circuit connection diagram in which the logical configuration of the unit stages 200 and 300 in FIG. ₁ is realized by an I ² L circuit.
1, the first collector 201a is the transistor 202
The second collector 201b is connected to the base of the transistor 203.
the first collector 202a of the transistor 202;
is connected to the base of the transistor 201,
The second collector 202b is a drive output terminal
_{The third} collector 202c is connected to the base of the transistor 204, the fourth collector 202d is connected to the base of the transistor 203, and the third collector 203c of the transistor 203 is connected to the base of the transistor 205. The fourth collector 203d is connected to the base of the transistor 202.

Furthermore, the first collector 204a of the transistor 204 is connected to the second bit output terminal _Q1 , the second collector 204b is connected to the base of the transistor 205, and the third collector 204b is connected to the base of the transistor 205.
4c is connected to the base of the transistor 203. A first collector 205a of the transistor 205 is connected to the base of the transistor 204, and a second collector 205b of the transistor 205 is connected to the base of the transistor 202.

The unit stage 300 includes transistors 301 and 3
02, 303, 304, and 305, and their interconnection is the same as that of the unit stage 200, but the third collectors 302c and 303c of the transistor 302 and the transistor 303 are commonly connected, and the transistor 203
(unit stage 200).

This means that the fourth and fifth output terminals of the NAND gate 22 in FIG.
This is equivalent to being connected to the output terminals of gates 31 and 32.

In FIG. 4, the 2nd bit drive output terminal ₁ is connected to the 3rd bit trigger signal input terminal, and although not shown, the 2nd bit output terminal ₂ is connected to the 3rd bit in FIG. is connected to input terminal ₃ of the same circuit as transistor 30
It is assumed that the collectors of transistors corresponding to transistors 102 and 103 in FIG. 2 are connected to the x line to which the base of No. 3 is connected.

However, since the collector is not a 4-bit configuration,
If the number of bits is large, _a circuit with the same configuration as the unit stage 300 shown in FIG. The same circuit configuration as in FIG. 2) is used.

Next, the operation shown in FIG. 4 will be explained with reference to the signal waveform diagrams shown in FIGS.

Now, the transistors 201, 204, 3 in FIG.
01,304 is "0" and the output levels of the other transistors are "1" at time _t11 .
The base level of 1 is “1” as shown in Figure 5 A.
When the level of the first collector 201a and the second collector 201b of the transistor 201 change to "1", the level of the transistor 201 changes to "1".

the first collector 201 of the transistor 201;
When the level of a shifts to "1", the level of the fourth collector 203d of the transistor 203 and the second collector 205b of the transistor 205 are both "1" in advance, so the level of the first collector 202a of the transistor 202 changes. “0”
Then, the levels of the second collector 202b, the third collector 202c, and the fourth collector 202d successively shift to "0".

the third collector 202 of the transistor 202;
When the level of c shifts to "0", the level of the first collector 204a of the transistor 204 shifts to "1", and then the level of the second collector 204b,
The level of the third collector 204c becomes “1” one after another.
to move to.

a second collector 204 of the transistor 204;
When the level of b shifts to "1", since the level of the third collector 203c of the transistor 203 has become "1" in advance, the level of the transistor 20
The level of the first collector 205a of No. 5 shifts to "0", and subsequently the level of the second collector 205b also shifts to "0".

the second collector 205 of the transistor 205;
When the level of b shifts to "0", the output level of the transistor 202 returns to "1", and the levels of the first collector 202a, the second collector 202b, the third collector 202c, and the fourth collector 202d increase one after another. and returns to “1”.

the first collector 202 of the transistor 202;
Assuming that the level of the trigger signal input terminal ₁ has shifted to "1" at the time when the level of a returns to "1", the levels of the first collector 201a and the second collector 201b of the transistor 201 will change one after another. Shifts to “0”.

On the other hand, immediately after time _t11 , the level of the second collector 202b of the transistor 202 shifts from "1" to "0", but this causes the levels of the first collector 301a and the second collector 301b of the transistor 301 to change. As the level of the first collector 301a of the transistor 301 shifts to "1", the transistor 30
2 first collector 302a, second collector 30
2b, the third collector 302c, the fourth collector 302d, and the fifth collector 302e transition to "0" one after another.

the fourth collector 302 of the transistor 302;
When the level of d shifts to "0", the level of the first collector 304a of the transistor 304 shifts to "1", and the levels of the second collector 304b and third collector 304c also shift to "1" one after another. Transition.

a second collector 304 of the transistor 304;
When the level of the transistor 305 shifts to "1", the levels of the first collector 305a, the second collector 305b, and the third collector 305c of the transistor 305 successively shift to "0", and the transistor 3
As the level of the third collector 305c of the transistor 305 changes to "0", the output level of the transistor 302 returns to "1", and furthermore, the output level of the transistor 302 returns to "1".
The output level of 01 shifts to "0".

By the way, at time _t12 in FIG. 5, the timing at which the level of the fourth collector 202d of the transistor 202 returns to "1" and the timing at which the level of the second collector 201b of the transistor 201 returns to "1" coincide. There is a good possibility that the time at which the output level of the transistor 201 becomes "0" is slightly delayed due to subtle variations in wiring capacitance and transistor characteristics.

Therefore, when the outputs of the transistors 302 and 303 constituting the next unit stage 300 are not applied to the base of the transistor 203, the output level of the transistor 202 is "1".
There is a risk that the output level of the transistor 203 will shift to "0" immediately after the transition to "0" (causing a malfunction).
In the interval indicated by A before and after _t12 , that is, in the interval in which the level of the third collector 302c of the transistor 302 is "0", the output level of the transistor 203 is prohibited from becoming "0". There is no risk of malfunction.

In addition, the base of the transistor 303 constituting the unit stage 300 is similarly connected to the output of the next stage circuit (here, since the next stage circuit has the same configuration as in FIG. 2, the output of the transistor 102 and the transistor 103 ) can prevent the transistor 303 from malfunctioning. (The signal waveform indicated by the dotted line in FIG.
These are signal waveforms appearing at the first collector 2a, the second collector 2b, the third collector 2c, and the fourth collector 2d of No. 2. ) In the unit stage 200, the fact that the first collector 202a of the transistor 202 is connected to the base of the transistor 201 creates a risk of such a malfunction. (The output level of transistor 201 becomes "0" after the output level of transistor 202 returns to "1".) There is another reason for the connection.

That is, the output signal appearing at the second collector 202b of the transistor 202 is supplied to the next stage as a drive signal, but if the connection is not made, the leading edge and trailing edge of the output signal of the transistor 202 are Both are regulated by the leading edge and trailing edge of the input trigger signal, making it impossible to supply a drive signal with a pulse width wider than the pulse width of the input trigger signal to the next stage.

As the trigger signal propagates through many unit stages in this state, the pulse width gradually becomes narrower due to wiring capacitance, load capacitance, etc., and eventually disappears.

In the circuit shown in FIG. 4, for example, to explain the unit stage 200, the transistor 202
By connecting the first collector 202a of the unit stage to the base of the transistor 201, at least the trailing edge of the drive signal supplied to the next stage is not restricted by the trailing edge of the input trigger signal, but the trailing edge of each transistor in the unit stage is In other words, even if the pulse width of the input trigger signal becomes extremely narrow, it is possible to widen the pulse width again within the unit stage and supply it to the next stage. The trigger signal does not disappear midway.

Now, when the leading edge of the input trigger signal arrives at time _t13 and the level of the base of the transistor 201 shifts to "0", the first collector 201a of the transistor 201 and the second collector
The level of the collector 201b shifts to "1", and at that point the level of the fourth collector 2 of the transistor 202 shifts to "1".
02d, third collector 20 of transistor 204
4c, furthermore, the level of the third collector 302c of the transistor 302 and the third collector 303c of the transistor 303 are all "1", so the output level of the transistor 203 shifts to "0", and the third collector 303c of the transistor 303 , the level of the fourth collector 203d shifts to "0" one after another.
(The first and second collectors of the transistor 203 are not used here.) The third collector 203 of the transistor 203
When the level of c shifts to "0", the output level of transistor 205 shifts to "1", and then the output level of transistor 204 shifts to "0".

On the other hand, when the trailing edge of the input trigger signal arrives at time _t14 , the transistor 2
Since the output level of the transistor 203 shifts to "0" and the level of the second collector 201b shifts to "0", the output level of the transistor 203 shifts to "1".

Note that before the level of the second collector 203b of the transistor 203 shifts to "1", the level of the first collector 201a of the transistor 201 shifts to "0", so at this point the output level of the transistor 202 changes. will not become "0" and cause malfunction.

At time _t15 , when the leading edge of the input trigger signal arrives, unit stage 200 operates in the same manner as at time _t11 , and transistor 2
02 supplies a drive signal to the next unit stage 300.

a second collector 202 of the transistor 202;
When the level of b shifts to "0", the output level of transistor 301 shifts to "1", then the output level of transistor 303 shifts to "0", and then the output level of transistor 305 shifts to "1". As a result, transistor 30
4's output level shifts to "0".

the third collector 304 of the transistor 304;
When the level of c shifts to "0", the output level of the transistor 303 returns to "1", and then the output level of the transistor 301 shifts to "0", and the series of operations ends.

At time _t16 , the second
At the same time as the level of the collector 201b shifts to "0", the fourth collector 20 of the transistor 202
2d has shifted to "1", but the unit stage 200 will not malfunction in this case as well, since the B period is the period in which the output level of the transistor 203 is prohibited from changing by the transistor 303.

In this way, the binary counter of the present invention can configure a unit stage with fewer gates than conventional ones, so if the present invention is applied to digital LSIs where many counter circuits are used, the chip size of the IC can be reduced. In addition, it is possible to reduce power consumption.

Furthermore, if the same power consumption as before is allowed per unit stage, the allowable power consumption per gate increases, so it is possible to operate at a higher frequency than before.

In the detailed explanation of the present invention, the effect of reducing the number of transistors is greatest (the conventional 7 transistors without the reset function are reduced to 5 transistors by applying the present invention) in the I ² L circuit. However, it goes without saying that the present invention is also effective when applied to ICs of other processes such as CMOS and nMOS.

Furthermore, the embodiments of the present invention are not necessarily limited to the circuit configurations shown in FIGS. 1 and 4, and various equivalent conversions and omissions can be made as necessary. For example, FIG. 6 shows an example in which the present invention is applied to a frequency divider, and each bit output terminal Q ₀ , Q ₁ ,
Q ₂ , ... are omitted, and the 5-input NAND gate 22
is replaced with a 4-input NAND gate 26, and in its place an AND gate 37 is added at the next stage.

In addition, in FIG. 6, unit stages 400, 50
0, . . . 800 have the same configuration as the unit stage 300, but since it is unlikely that the trigger signal generated by the unit stage 300 disappears on the input side of the unit stage 400, the unit stage The present invention is applied only to unit stage 500 and unit stage 700, and the remaining unit stages are
A simpler configuration as shown in the figure is also possible.

For the same reason, the MSB does not necessarily have the same configuration as the unit stage 900 in FIG.
If a trigger signal to be applied to other circuits is not extracted from the MSB, the configuration of the MSB shown in FIG. 7 is sufficient.

Furthermore, a reset or preset function for each unit stage can be added as necessary.

For example, in FIG. 4, the unit stage 200,
To reset 300, connect the collector of a reset transistor (not shown) to the bases of transistors 205 and 305, and to preset to [1, 1], connect the collector of a reset transistor (not shown) to the bases of transistors 205 and 305. It is sufficient to connect the collectors of the transistors 204 and 304 to the bases of the transistors 204 and 304.

In addition, in the logical configuration diagrams of Figures 1 and 6,
Although NAND gates and AND gates are used, other matching gates such as NOR gates and OR gates can also be used.

As described above, in its logical configuration, the binary counter of the present invention has a first match gate pair (20
a second matching gate pair (corresponding to 202) comprising a third and fourth matching gate; 5 matching gates (corresponding to the NAND gate 25), and the first and second matching gates are connected to second input terminals of the third and fourth matching gates, respectively.
a third input terminal of the first and second match gates, respectively, an output signal of the second match gate pair; a trigger signal from the previous stage is supplied to one input terminal, an output signal of the first coincidence gate is supplied to a second input terminal of the fifth coincidence gate, and is supplied as a trigger signal to the next stage; The first to fifth coincidence gates constitute a unit stage, and the first and second coincidence gates constituting the next unit stage are connected to the fourth and fifth input terminals of the second coincidence gate, respectively. It is configured to supply the output signal of the coincidence gate, and
It is possible to configure a unit stage with a smaller number of logic gates than before, and as a result, it has great effects such as reducing IC chip size and power consumption.

[Brief explanation of the drawing]

FIG. 1 is a logical configuration diagram of a binary counter according to an embodiment of the present invention, FIG. 2 is a circuit connection diagram in which the unit stage 100 of FIG. 1 is configured with an I ² L circuit, and a to u in FIG. The signal waveform diagram of each part in Fig. 2, and Fig. 4 are the unit stages 200 and 30 of Fig. 1.
0 is a circuit connection diagram composed of an I ² L circuit, A to M in Fig. 5 are signal waveform diagrams of each part in Fig.
FIG. 7 is a logical configuration diagram showing another embodiment of the present invention.
The figure is a logical configuration diagram showing another example of the configuration of the unit stage. 100, 200, 300, 400... unit stage, 201, 202... gate pair.

Claims (1)

[Claims] 1. A first matching gate pair including first and second matching gates whose respective first input terminals and output terminals are cross-coupled, and a third and fourth matching gate pair. a second match gate pair; and a fifth match gate for applying an output signal to second input terminals of the first and second match gates;
supplying the output signals of the first and second coincidence gates to second input terminals of the coincidence gates, respectively; a trigger signal from a previous stage to a first input terminal of said fifth coincidence gate; and an output signal of said first coincidence gate to a second input terminal of said fifth coincidence gate. It is supplied to the input terminal as well as to the next stage as a trigger signal, and the first, second, third, fourth and fifth
A unit stage is formed by the matching gates, and the output signals of the first and second matching gates forming the next unit stage are inputted to the fourth and fifth input terminals of the second matching gate, respectively. A binary counter configured to supply 2. The third input terminal of the first coincidence gate is connected to the output terminal of the fourth coincidence gate, and the third input terminal of the second coincidence gate is connected to the third input terminal of the second coincidence gate. is connected to the output terminal of the third coincidence gate.