JPS6397037A - Loop network system - Google Patents

Abstract

PURPOSE:To access with no waiting by accessing a local memory from a CPU in case a controller detects that a memory bus is not being used and is vacant. CONSTITUTION:In case of accessing the local memory 40 from the CPU, a memory interface control circuit 30 receives with its bus monitoring circuit 31 a memory access information 201 from the controller 20. The monitoring circuit 31 detects a period during which the memory bus 202 is being used and a period the bus 202 is not being used for the sake of transmission/reception processing of a network data, and informs a bus control circuit 32 of the period when the bus 202 is not being used. The circuit 32 controls a memory interface circuit 34 to release the bus 202 for the CPU during the period when the bus 202 is not used. Thus, the circuit 34 release the bus 202 for the CPU, and the CPU accesses the local memory 40. Since the access to the memory 40 from the CPU is executed apart from the controller 20, the said access is executed without any waiting.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a loop network system comprising nodes connecting terminals and the like and transmission lines connecting the nodes in a loop.

Conventional technology FIG. 4 shows a configuration diagram of the loop network system.

In FIG. 4, nodes 1 to 4 are connected in a loop through a transmission line 1oo made of optical fiber or coaxial cable. In the nodes 1 to 3, the transmission line 1
Reception of network data from 00 and transmission path 1
In order to transmit network data to 00 and access local memory from the CPUs in the nodes 1 to 4, the nodes 1 to 4 have conventionally been configured as shown in FIG. For example, Intel Corporation, LAN Components User Manual 230
814-001 etc.).

In FIG. 3, node 1 includes cptzo, controller 20. A system bus 90 that connects the CPU 10 and the controller 2o. a local memory 40 and a memory bus 20 connecting the controller 20 and the local memory 40
Consists of 2. When receiving network data from the transmission path 100, the controller 20 that has received the received network data performs reception processing, acquires the memory bus 202 based on the arbitration function of the memory bus 202 in the controller, and stores the data in the local memory 40. The received network data is written to. Furthermore, when transmitting network data to the transmission path 1oO, the controller 2o transmits data based on the transmission request from the OPU IQ obtained via the system bus 90.
Based on the arbitration function of the memory bus 202, network data to be transmitted is transferred to the local memory 4o.
After being read out and subjected to transmission processing within the controller 2o, it is sent out to the transmission path 10o. Next, 0PTJ1
When accessing local memory 4o from ゜, CP
The local memory 4o access request signal from U1o is
It is sent to the controller 2o via the system bus 9o. Upon receiving the access request signal to the local memory 4o of CpTJlo, the controller 20 arbitrates the memory bus 202 in the transmission/reception process.
Arbitration of the memory bus 202 is performed in response to a local memory 40 access request signal from the CPU 10. As a result, cptzo can access the local memory 4o only when the memory bus 202 is acquired for access from the CPU 10. The arbitration function of the memory bus 202 is configured by several stages of latches and logic. Therefore, the CPU
In order to acquire the memory bus 202 in order to access the local memory 40 from QPUl 0, it passes through several stages of latches and multiple stages of logic, so there is a wait when accessing the local memory 40 from QPUl 0. This is not a problem when it comes to small-capacity network data, but it becomes a big problem when it comes to large-capacity network data.

Problems to be Solved by the Invention Conventionally, when the CPU accesses the local memory, the CPU acquires the memory bus based on the memory bus arbitrage control function in the controller. It becomes possible. The Arbitration function of the memory bus is
Since it is composed of several stages of latches and logic, the CP
When accessing local memory from U, the request signal passes through several stages of latches and logic, so the CPU
A wait is added to local memory access from . This poses a major problem when it comes to transmitting large amounts of network data.

Means for Solving the Problems The present invention solves the above-mentioned problems, and includes a memory interface control circuit inside a node to control access information to the local memory of the controller associated with network data transmission/reception processing. Based on this, the memory interface control circuit monitors the state of access to the local memory from the controller, and if the controller does not access the local memory and detects that the memory bus is empty, CPtT
o from the CPU by releasing the memory bus for
- By enabling access to local memory,
It is possible to access the local memory from the C1PU without waiting.

As described above, the present invention includes a memory interface control circuit in addition to a CPU, a controller, and a local memory inside a node constituting a loop network system, and uses the memory interface control circuit for processing network data transmission and reception. Based on the controller's access information to the controller, the memory interface control circuit monitors the access state of the controller to the local memory to detect that the controller is not accessing the local memory and the memory bus is empty. In this case, by releasing the memory bus to the CPU and allowing the CPU to access the local memory, the CPU can access the local memory without waiting.

Example FIG. 1 shows an embodiment of the present invention.

In FIG. 1, node 1 has CPU 10. Controller 20. Memory interface control circuit 3Q, CPU10
and controller 2o and memory interface control circuit 3
0 system bus 90. It is composed of a local memory 40 and a memory bus 202 that connects the memory interface control circuit 30 and the local memory 4o.

Regarding the reception of network data from the transmission path 100 and the transmission of network data to the transmission path 10o, the memory bus 2 inside the controller 20 is used as in the past.
02, the local memory 40 is accessed via the interface 200 with the memory interface control circuit 30. At this time, the controller 20 requests the memory interface control circuit 30 to use the memory bus to access the local memory 4o in order to receive network data from the transmission path 1oO and transmit network data to the transmission path 100. memory access information 201 indicating that the

When the local memory 4o is accessed from the CPU 1°, if the memory interface circuit 3o detects that the memory bus 202 is not in use based on the memory access information 201, the memory bus 202
The CPU 10 releases the local memory 40 for access, allowing the CPU 10 to access the local memory 40.

FIG. 2 shows a configuration diagram of the memory interface control circuit 3°. In FIG. 2, the memory interface control circuit 30 includes a bus monitoring circuit 31, a bus control circuit 32, an XA
It is composed of a CK generation circuit and a memory interface circuit 34. When the local memory 40 is accessed from the CPU 1o, the memory interface control circuit 30 uses the memory access information 2 from the controller 20.
01 is received at the bus monitoring circuit 31. Upon receiving the memory access information 201, the bus monitoring circuit 31 detects the periods in which the memory bus 202 is used for transmitting and receiving network data to and from the transmission line 100, as well as the periods in which it is not used, and performs bus control. circuit 32
, the period during which the memory bus 202 is not used. The bus control circuit 32, which has received the memory path 202 unused period notification from the bus monitoring circuit 31, controls the memory interface circuit 34 to release the memory bus 202 to CPLTlo while the memory path 202 is unused. and the XACK generation circuit 33
, and notifies that the memory bus 202 has been acquired.

A memory interface circuit 34, which is controlled by the bus control circuit 32 to enable access from the CPU 10 to the local memory 40, connects the memory bus 202 to the CPU.
10, and the CPU 10 accesses the local memory 4o based on this. In addition, the XACK generation circuit 33 that has received the acquisition notification of the memory bus 202 sends a message to the CPU 10 based on the bus cycle of the system bus 90.
A response signal, XACK, is sent via the system bus 90. As described above, according to the present invention, since the access from the CPU 10 to the local memory 40 does not pass through the controller 20, the access from the CPU 10 to the local memory 40 can be executed without waiting.

Effects of the Invention As described above, according to the present invention, the memory interface control circuit monitors the state of access from the controller to the local memory based on the memory access information from the controller to the local memory associated with network data transmission/reception processing. If the controller detects that the memory bus is not in use and is free, it releases the memory bus to cpv.
By enabling access from the PU to the local memory, it is possible to access the local memory from the CPU without waiting.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a node showing an embodiment of the present invention, and FIG.
FIG. 3 shows a block diagram of a memory interface control circuit, FIG. 3 shows a block diagram of a node in a conventional method, and FIG. 4 shows a block diagram of a loop network system. 1...No)", 10...CPU, 2
0... Controller, 30... Memory interface control circuit, 4o... Local memory, 90... System bus, 10o...
...Transmission path, 20o... Controller/memory interface control circuit interface, 201...
...Controller memory access information, 202...
...Memory bus.

Claims (1)

[Claims] It consists of a node that connects terminals, etc., and a transmission line that connects the nodes in a loop, and the node is equipped with a CPU, a controller, a local memory, and a memory interface control circuit, and is equipped with a CPU, a controller, a local memory, and a memory interface control circuit. Based on the sent memory access information indicating the controller's real-time access to the local memory, the memory interface control circuit monitors the access state from the controller to the local memory, so that the controller When it is detected that the memory bus is free without accessing the local memory, the memory bus is released to the CPU, thereby allowing the CPU to access the local memory. A loop network system that allows the CPU to access the local memory without waiting.