JPS6396962A - Fieid-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the mutual conductance of a field effect transistor while alleviating the electric field intensity of a channel region by increasing the impurity concentration of the channel region from a source toward a drain. CONSTITUTION:A channel region 2 in which an N-type impurity is doped is formed on a semiconductor insulating substrate 1 made of gallium oxide or the like, a gate 3 is formed thereon, source, drain N-type high concentration impurity regions 4a, 4b are formed on the gate 3 in a self-aligning manner, and source and drain electrodes 5a, 5b are provided thereon to form an FET. The impurity concentration of the region 2 is raised from the source to the drain, a depleted layer is extended more toward the drain to alleviate an electric field intensity in the region 2, and its absolute value increases more toward the drain. As a result, mutual conductance gm is increased to form an FET having high performance at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Differential Fields of Application J] The present invention relates to a field effect transistor and a method for manufacturing the same, and particularly relates to a field effect transistor having a Schittky junction or PN junction gate and a method for manufacturing the same.

[Conventional technology]

It is known to construct a field effect transistor by providing a Schittke junction type or PN junction temperature gate on an active layer of a semiconductor, and further providing source and drain electrodes.

FIG. 6 is a schematic cross-sectional view of an example of a conventional FET.

In this example, a channel region 2' uniformly doped with n-type impurities is provided on a semi-insulating substrate 1, and the channel region 2'
A semiconductor gate 3 is provided on top of the gate 3, and high-concentration impurity regions 4a and 4 are formed on both sides of the channel region 2'.
b is provided, and source and drain electrodes 5a and 5b are further provided thereon.

Therefore, is there a depletion layer due to the Shimettky junction? ′ expands,
l electrons travel through the channel region 2' as if weaving through it.

The operating state yi of this embodiment will be explained below.

First, as shown in FIG. 6, with the source end of gate 3 as the origin and the X axis in the direction of the drain, the potential of gate 3 is set to O.
The potential V(X) in the channel region at xK can be expressed by the gradient of the depletion atomizer at the coordinate X. Here, q is the absolute value of the electron charge, n (> is the impurity concentration of the channel region 2', t is the thickness of the channel region 2', e is the relative dielectric constant 'F!L ratio, eo
is the dielectric constant of vacuum, and VP is the pinch-off voltage.

Also, the maximum drain current ID8 flowing between the source electrode 5a and the drain electrode 5b is IDs = noq (t-scorn)μlIW=n0q
(t-aL)7*ESW-...(31=noq
(t-a6)a Eo W is given. Here μ
is the electron mobility, W is the gate width, E (X) is the electric field strength in the channel region 2' at the coordinate The electric field strength aL at 0) is the expansion of the depletion layer at the drain end (X=L), and ao is the expansion of the depletion layer at the source end (x=o).

Further, the barrier voltage Vbi of the Schittky junction can be expressed as follows.

Furthermore, the electric field strength E in the channel region 2') is equal to the potential V (
There is a relationship with chrysanthemums.

FIGS. 7(JL) and (b) are respectively a distribution diagram of the expansion of the depletion layer in the channel region of FIG. 6 and a distribution diagram of the electric field strength.

As shown in Figure 7(a), when the depletion layer expands to 1 m),
Since the size increases from the source side to the drain side, the channel becomes narrower toward the drain side.

Furthermore, the electric field strength E) increases rapidly as it approaches the drain side, as shown in FIG. 7 Φ).

Here, the physical constant used in the numerical calculation is gallium arsenide FE
Assuming T, select no=IX10 cm #=13.0 L=1.0 μm Es=3KV/m t=α1 μm tt = 5ooocd7v, See, and barrier voltage Vbi is pinch-off voltage Vp (=
Set to 1/3 of 0.7V).

Furthermore, the mutual conductance gm of the FET is given by -al = 2g#0μmEs-@((3). From this, when determining the semiconductor material, in order to obtain a large mutual conductance gm t-, the electric field strength Eo at the source end must be It can be seen that the closer the electric field strength is to E8, or the smaller the spread of the depletion layer at the drain end, the better.

[Problem that the invention seeks to solve]

However, in conventional field effect transistors, the impurity concentration in the channel region is uniform from the source end to the drain end, so the depletion layer in the channel region expands wider as it approaches the drain side. There is a drawback that the absolute value of the electric field strength E in the drain side root channel region becomes large, making it difficult to improve the mutual conductance gm.

An object of the present invention is to provide an FET in which the electric field strength in the channel region is relaxed and the mutual conductance gm is increased, so that the performance is further improved.

[Means for Solving the Problems] The field effect transistor of the present invention has a low concentration channel region of one conductivity type provided on the surface of a semi-insulating substrate, a gate provided on the channel region, and a conductive layer formed on the surface of the semi-insulating substrate through the channel region. In a field effect transistor comprising connected high concentration source and drain regions of one conductivity type, the impurity concentration of the channel region increases from the source side to the drain side@field effect transistor of the present invention The manufacturing method includes a low concentration channel region of one conductivity type provided on the surface of a semi-insulating substrate, a gate provided on the channel region, a high concentration source of one conductivity type connected through the channel region, and a gate region provided on the channel region. In the method of manufacturing a field effect transistor having a drain region, impurities in the drain region are removed by a step of forming at least the drain region of one conductivity type concentration continuous with the channel region on the surface of the semi-insulating substrate and heat treatment. The method includes a step of diffusing into a channel region to form the channel region in which the impurity concentration increases from the source side to the drain side.

[Effect]

In the present invention, the maximum drain current can be increased without decreasing the impurity concentration in the channel region, and the mutual conductance gm can be increased to improve performance.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of an embodiment of the FET of the present invention.

In this embodiment, a channel region 2 doped with n-type impurities is provided on the surface of a semi-insulating substrate 1 made of gallium arsenide, a gate 3 is provided in this channel region 2, and the nfi height of the source and drain is self-aligned to the gate 3. High concentration impurity regions 4a and 4b are provided, and source and drain electrodes 5 are further formed thereon.
A and 5bt- are provided, and the impurity concentration of the channel region 2 increases from the source side to the drain side.

FIGS. 2(a), 2(b), and 2(c) are distribution charts of the impurity concentration, depletion layer expansion, and electric field strength in the channel region of FIG. 1, respectively.

In this embodiment, the impurity concentration n (x
), and the impurity concentration increases from the source toward the drain as shown in FIG. 2 (1).

In addition, as in the conventional example, when the barrier voltage Vbi is set to Vincio and the potential of the gate 3 is 0, the depletion layer wave at the coordinate X is □
n(gona(God8...(8)2εtO).On the other hand, from the maximum drain current, s is I
O3-(in(X) (t-a(d)μE(x) W
---(9) becomes. Here, Ig(sl = Es... (11)
Using the same physical constant values and impurity concentration slope value λ=0.25 as in the conventional example, the numerical hand 31. t- Then,
The expansion of the depletion layer, shea (x), and the electric field strength E(-4) are as shown in FIGS. 2(b) and 2(e), respectively.

FIG. 3 is a maximum drain current characteristic diagram with respect to the slope of impurity concentration in the channel region.

Here, the maximum drain current Ins is normalized by the drain current Ingo = noqμEstW, and the broken line indicates the normalized maximum drain current when the electric field becomes Es at the source end, and the maximum drain current at that time is Ic. Then, it becomes .

Next, comparing the electric field strength E (gradient) in the channel region of the FET of the embodiment of the present invention and the conventional example with reference to FIG. 2(e) and FIG. 7 (noodle), the electric field strength at the drain end is , to cause electron velocity saturation, both are the same as Es, but the electric field strength at the source end is α75 Es in the embodiment of the present invention, which is L5 times larger than 0.5 Es in the conventional transistor.

Therefore, since the maximum drain current ID8 is equal to nQ for both transistors with impurity concentration at the source end, the embodiment of the present invention is about L5 times larger than the conventional example.

Similarly, at the drain end where velocity saturation occurs, the channel thickness t
-ILL) is 0.25t in the embodiment of the present invention and α21t in the conventional example, which is larger than the conventional example, and the impurity concentration at the drain end is also higher than that of the conventional example.
In the example of the present invention, the maximum drain current is 125 times higher, so it can be seen that the maximum drain current increases as the impurity concentration ratio on the drain side increases.

This corresponds to the fact that the electric field strength at the source end increases with λ. However, in the embodiment of the present invention in which the impurity concentration is provided with a uniform slope, it is impossible to reduce λ by α48.

Furthermore, in the embodiment of the present invention, the impurity concentration at the source end is nQ as in the conventional example, so as shown in FIG. You can see that it increases.

FIG. 4(a) to (ψ are the first values of the manufacturing method of the 0FET of the present invention.
FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

In this embodiment, first, as shown in FIG. 4, an active layer 2af doped with NFI impurities is epitaxially grown on a semi-insulating substrate 1 of gallium arsenide.

Next, as shown in FIG. 4(b), after forming a gate 3 made of tungsten silicide (WSi), a photoresist film 6 is formed to provide an opening for forming a drain impurity region, and this is further used as a mask. , silicon, which is an N-type dopant, is ion-implanted.

Next, as shown in FIG. 4C, after removing the photoresist film 6, a nitride film 7 is deposited on the entire surface, and ion implantation of impurities is performed. At this time, the ion-implanted impurity is diffused laterally, and the impurity concentration of the active layer 2a under the gate 3 can be increased from the source side to the drain side.

Finally, as shown in FIG. 4 (Φ), after forming the nitride film 7t-t, an impurity region 4b is formed in a self-aligned manner on the gate 3.
Furthermore, gold, germanium, nickel (Au, Go-Ni)
The FE according to the first embodiment of the present invention is formed by forming source and drain electrodes 5a and 5b consisting of
I can do T.

FIGS. 5(a) to 5(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a second embodiment of the method for manufacturing an 0FET according to the present invention.

In this embodiment, first, as shown in FIG. 5(a), an active layer 2a doped with an N-type impurity is epitaxially grown on a semi-insulating substrate lO of gallium arsenide.

Next, as shown in FIG. 5(b), after forming a gate 3 made of 1 tungsten silicide (ws i ),
A photoV-) film 6 is formed, a window for forming a drain impurity region is opened, and silicon, which is an N-type dopant, is ion-implanted using this as a mask.

Next, as shown in FIG.
Silicon, which is a type dopant, is ion-implanted to a low concentration in the drain region as well.

Next, as shown in FIG. 5 (Φ), a dosing film 7 is deposited on the entire surface and ion-implanted impurities are applied to the channel region 2 and the source and drain impurity regions 4a and 4b'.
form. At this time, in this annealing process, the implanted impurities are activated and laterally diffused into the channel region 2 below the gate 3. However, since the impurity ion-implanted into the drain region 4b' has a higher concentration than the impurity ion-implanted into the source region 4a, the impurity concentration in the channel region 2 under the gate 3 is changed from the source side to the drain side. can be made higher.

Finally, as shown in Figure 5<6), after removing the nitrided rA7, gold/germanium/nickel (Au/Gell
N1) source and drain electrodes 5a and 5bt
- The FET according to the second embodiment of the present invention can be obtained by forming and heat-treating.

In the FET according to the second embodiment, since the channel region of the source is also highly doped compared to the case of the first embodiment, the contact resistance with the source electrode is small, and therefore the source parasitic resistance is low. High performance FET can be realized.

〔Effect of the invention〕

As explained above, in the present invention, by increasing the impurity concentration in the channel region from the source toward the drain, the maximum drain current ID3 can be increased without significantly changing the total pitch-off voltage, and the mutual conductance can be increased. Since it is possible to improve the gm, there is an effect that a field effect transistor with excellent driving ability, high speed, and high performance can be realized.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of one embodiment of the FET of the present invention, and FIGS. 2 (=), (b), and (C) show the impurity concentration of the channel region and the expansion of the depletion layer shown in FIG. 1, respectively. 3 is a cross-sectional view of a semiconductor chip shown in order of steps to explain the first and second embodiments of the method for manufacturing impurities in the channel region, and FIG. 6 is an example of a conventional 0FET. FIGS. 7A and 7B are schematic cross-sectional views of FIGS. 7A and 7B, which are distribution diagrams of the depletion layer expansion and electric field strength in the channel region of FIG. 6, respectively. 1...-Semi-insulating substrate, 2,2'...channel region, 2 &-----active layer, 3--------
Gate, 4a, 4b. 4b/... impurity region, 5t... source electrode, 5b... drain electrode, 6......
・Photoresist film, 7... Nitride film, 8...
-・Photoresist film, 9.9'... Depletion layer, a
)...--The depletion layer expands, E), E
...Electric field strength, IC9ID! ...Maximum drain current, ID30...Drain current, L...
...Gate length, n(X). ng...Impurity concentration, t...Thickness of the channel region, 稟f Figure χNa x77 Kaya 7 times

Claims (2)

[Claims] (1) A low concentration channel region of one conductivity type provided on the surface of a semi-insulating substrate, a gate provided on the channel region, and a high concentration source and drain region of one conductivity type connected through the channel region. 1. A field effect transistor comprising: an impurity concentration in the channel region that increases from the source side toward the drain side. (2) A low concentration channel region of one conductivity type provided on the surface of a semi-insulating substrate, a gate provided on the channel region, and a high concentration source and drain region of one conductivity type connected through the channel region. In the method for manufacturing a field effect transistor, impurities in the drain region are removed from the channel region by a step of forming at least the drain region of one conductivity type and high concentration that is continuous with the channel region on the surface of the semi-insulating substrate and by heat treatment. 1. A method of manufacturing a field effect transistor, comprising the step of diffusion to form the channel region in which the impurity concentration increases from the source side to the drain side.