JPS6393646U - - Google Patents

Info

Publication number
JPS6393646U
JPS6393646U JP18936286U JP18936286U JPS6393646U JP S6393646 U JPS6393646 U JP S6393646U JP 18936286 U JP18936286 U JP 18936286U JP 18936286 U JP18936286 U JP 18936286U JP S6393646 U JPS6393646 U JP S6393646U
Authority
JP
Japan
Prior art keywords
semiconductor pellet
semiconductor
molded
covered
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18936286U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18936286U priority Critical patent/JPS6393646U/ja
Publication of JPS6393646U publication Critical patent/JPS6393646U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る半導体装置の部分平面図
、第2図は従来の半導体装置の部分平面図である
。 16…半導体ペレツト、18,18…端子、2
0…Cu配線、22…外装樹脂材。
FIG. 1 is a partial plan view of a semiconductor device according to the present invention, and FIG. 2 is a partial plan view of a conventional semiconductor device. 16... Semiconductor pellet, 18, 18... Terminal, 2
0...Cu wiring, 22...Exterior resin material.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体ペレツトを含む主要部分を外装樹脂にて
モールド被覆したものにおいて、上記半導体ペレ
ツトの回路の一部を基板上に設けたことを特徴と
する半導体装置。
1. A semiconductor device in which a main part including a semiconductor pellet is molded and covered with an exterior resin, wherein a part of the circuit of the semiconductor pellet is provided on a substrate.
JP18936286U 1986-12-08 1986-12-08 Pending JPS6393646U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18936286U JPS6393646U (en) 1986-12-08 1986-12-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18936286U JPS6393646U (en) 1986-12-08 1986-12-08

Publications (1)

Publication Number Publication Date
JPS6393646U true JPS6393646U (en) 1988-06-17

Family

ID=31141593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18936286U Pending JPS6393646U (en) 1986-12-08 1986-12-08

Country Status (1)

Country Link
JP (1) JPS6393646U (en)

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