JPS6393058A - Cache memory system - Google Patents

Abstract

PURPOSE:To attain the effective availability of the full capacity of a cache memory by selecting bits after comparing a real address given from an associative memory with that given from a cache directory. CONSTITUTION:When a cache memory 4 and a cache directory 3 receive access at a real address part in a logical address, the least significant bit of a main address received from an associative memory 2 is invalidated or validated through an AND gate 5 according to a prescribed page size or a half page size. The real addresses read out of the memory 4 and the directory 3 are compared with each other by a comparator 21. When no coincidence is obtained between both real addresses, a FF 10 inverts its holding value to obtain the most significant value bit that gives access to the memory 4 and the directory 3. While the held value is used to access again in the case of a half page size.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to cache storage processing in a virtual storage system, and in particular to a cache storage system that allows the entire cache storage capacity to be used even when the page size is halved. Regarding the method.

(Prior Art) Conventionally, in this type of cache storage method, under the management of an operating system that operates with a certain page size, the system is configured to be optimally configured for access with that page size. has been done. therefore,
When the page size is halved, if the cache memory and cache directory are accessed only by the real address part of the logical address that is the requested address, only half of both the cache memory and the cache directory can be used.

(Problems to be Solved by the Invention) In the conventional cache storage method described above, when the page size is halved, the cache storage and cache directory are stored only in the real address part of the logical address that is the requested address. When accessing, only half of both the middle Yash memory and the middle Yash directory can be used.
There are six drawbacks that reduce the efficiency of the system.

An object of the present invention is to have an address conversion means for converting a logical address into a real address, and also to have a cache memory, a cache directory, and an associative memory, and to convert the cache memory and the cache directory in the real address part of the logical address. When accessing , the least significant bit of the actual address is disabled or enabled depending on whether the page size is a predetermined size or half the size, and the page size is read from the associative memory. The address is compared with the real address read from the cache directory, and if the comparison result does not match, the held value is inverted, and the page size is halved as the most significant bit of the address that accesses the cache memory and cache directory. When the size of the page is half, the above disadvantage is removed by using the retained value, and when a mismatch is detected in the above comparison when the page size is half, the inverted value is used for the most significant bit. An object of the present invention is to provide a cache storage system configured so that cache storage and a cache directory can be accessed again using an address.

(Means for Solving the Problems) A cache storage system according to the present invention includes a cache storage, a cache directory, an address register, an associative memory, an access means, a valid/invalid selection means,
It is constructed by comprising a comparison means, a 7-rib flop, and a bit selection means.

Cache storage is for storing data in blocks.

The cache directory is a rounded directory that holds a portion of the main memory address corresponding to the unit data block stored in the cache memory.

The address register is for storing a logical address that is a request address for accessing the main memory.

The associative memory is for registering part of the correspondence between logical addresses and real addresses on main memory.

The access means is for accessing the cache memory and the cache directory by referring to the cache memory, the address directory, and the associative memory in parallel, and using the real address part of the logical address that is not subject to address translation.

The valid/invalid selection means is for invalidating or validating the least significant bit of the real address read from the associative memory depending on whether the page size is a predetermined page size or a half page size.

The comparison means is for comparing the real address read from the associative memory and the real address read from the cache directory.

The clip-flop is for inverting the held value when the comparison result of the comparison means is a mismatch.

The bit selection means uses the most significant bit of the real address portion of the logical address when the page size is a predetermined page size as the most significant bit of the address for accessing the cache storage and cache directory, and selects the most significant bit of the real address part of the logical address when the page size is a predetermined page size. Sometimes it is to use a value held by a flip-flop.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an explanatory diagram showing the contents of an address register that stores logical addresses according to the present invention.

In FIG. 1, 1 is an address register of a logical address which is a request address for accessing the main memory;
1 is the virtual address part of 7, and 12 to 14 are the real address parts thereof, but the real address part 12 becomes the virtual address part when the page size becomes half the size.

Hereinafter, the operation when the page size is reduced to half will be explained.

FIG. 2 is a block diagram showing one embodiment of the cache storage method according to the present invention. In the wL2 diagram,
1 is an address register, 2 is an associative memory, 3 is a cache directory, 4 is a cache memory, 5 to 8 are AND gates, 9 is an OR gate, ]0 is a 7 lip-flop, and 20.degree. and 21 are comparison circuits, respectively.

In Figure 2, the contents of address register 1 12.13
are for accessing the middle guy 75-memory 4 and the cache directory 3, respectively, and the content 14 is used to specify data within a unit block of the cache storage 4. In the associative memory 2, a part of the correspondence between logical addresses and virtual addresses is registered in order to perform address conversion at high speed. The least significant bit 210 of the real address read from the associative memory 2 is added to the AND gate 5 together with the 1/2 page size mode number on the signal ff1J150 to obtain a logical product. by this,
For a given page size, the least significant bit 210 on signal line 21G is ignored.

The cache directory 3 holds a portion of main memory addresses corresponding to unit data blocks stored in the cache memory 4. By referring to the cache directory 3 during cache access,
It is possible to know whether or not there is valid data in the cache memory 4.

The unit data block is a transfer point when data is transferred from the main memory to the cache memory 4.

AN according to the 1/2 vege mode code on the signal line 150
D gates 6 to 8 and OR gate 9 determine the address for accessing cache directory 3 and cache storage 4. That is, when the page size is a predetermined size, addresses 12 and 13 are used, and when the page size is half, the value held in the flip-flop 10 and the address 3 are used. The cache miss signal on signal line 120 causes the clip-flop to
Values held at 0 are inverted.

When a request source requests data based on the logical address number of the address register 1, a part of the virtual address section 11 is sent onto the signal line 220, the associative memory 2 is accessed, and the data is sent onto the signal line 221. The comparator circuit 20 compares the remainder of the virtual address section 11 with the virtual address section 211 read from the associative memory 2 .

If both of the above match, a TLB hit on the signal line 11G is sent. If the two do not match, the virtual address section 12 is converted into a real address by the address conversion means and registered in the associative memory 2 together with a part of the logical address.

The intermediate directory 3 is accessed using the value held in the clip flop 10 and the real address 13. Therefore, the real address read onto the signal line 230 and the real address read onto the signal line 231 from the associative memory 2 are compared by the comparison circuit 21. If the two match, the necessary data is read from the intermediate memory 4 and sent to the request source via the signal line 40.

If they do not match, there is a cache miss, and the value held in the cache clip 70 block 10 is inverted by the intermediate cache miss hit signal on the signal line 120. Once again, the cache directory 3 is accessed using the value of the 7-rig flop 10 and the real address 13. At the same time, the main memory is also accessed by the real address on the signal line 231 and the address section 13.

If the cache miss occurs during the second cache access, the signal is sent from the main memory via the signal line 130 to the signal line 24.
The unit data block is transferred to 0, and the necessary data is sent to the request source via signal line 140. At the same time, the above data is registered in the corresponding block on the cache memory 4. In this case, even if there is a cache miss, the value held in the clip hoop 10 is not inverted.

If a cache hit occurs on the second cache access, the access to main memory is immediately canceled.
Necessary data is sent from the cache memory 4 to the request source via the signal line 40. Since main memory access takes a longer time than cancel access, access to main memory can be canceled by the second access.

(Effects of the Invention) As explained above, the present invention provides that when accessing a cache memory and a cache directory, the page size is read from the associative memory depending on whether the page size is a predetermined size or half the size. Disable or enable the least significant bit of the real address, compare the real address read from the associative memory with the real address read from the cache directory, and invert the held value if the comparison result does not match; When the page size is half the size, the value stored above can be used as the most significant bit of the address for accessing the cache memory and the guard directory. Even if the page size is halved with the configured cache storage, the full capacity of the cache storage can be used effectively and system efficiency can be prevented from decreasing.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing logical addresses when the page size is half the size. FIG. 2 is a block diagram showing an embodiment of the 1,000-by-7 storage method according to the present invention. ]1111・Address register 2・・ΦAssociative memory 3・Cache directory 4 Keiken II+? Yatsushi memory S~8...AND gate 9, fist, OR gate 10...Flip 70 knobs 11-14...Address section 20.21-...Comparison circuit

Claims (1)

[Claims] A cache memory for storing data in block units, a cache directory for holding a part of the main memory address corresponding to the unit data block stored in the cache memory, and a request for accessing the main memory. an address register for storing a logical address that is an address; an associative memory for registering a part of the correspondence between the logical address and a real address on the main memory; the cache storage; the cache directory;
and access means for referencing the associative memory in parallel and accessing the cache storage and the cache directory using a real address part of the logical address that is not subject to address translation, and a page size that is a predetermined page size. or a half page size, valid/invalid selection means for invalidating or validating the least significant bit of the real address read from the content addressable memory, and the real address read from the content addressable memory and the cache directory. a comparison means for comparing real addresses read from the memory; a flip-flop for inverting a held value when the comparison result of the comparison means does not match; and an address for accessing the cache memory and the cache directory. When the page size is the predetermined page size, the most significant bit of the real address portion of the logical address is used as the most significant bit of the page size, and when the page size is half the page size, the value held by the flip-flop is used. 1. A cache storage system comprising: bit selection means for use.