JPS6393056A - Microprogram control system - Google Patents

Abstract

PURPOSE:To improve the availability of a microprogram control system by putting a switch instruction between a ROM and a RAM into a microinstruction and performing switch between the RAM and the ROM reading out the microinstruction to ensure free switching between the ROM and the RAM. CONSTITUTION:An address signals received from a microaddress register 1 are supplied to a ROM 4 and a RAM 5 and a microinstruction stored in an address is read out of the ROM 4 or the RAM 5 that is set under active state by the output of a chip selecting part 3. Then the read microinstruction is stored in a microinstruction register 6. The microinstruction includes a ROM/ RAM switching bit 7 to show whether the ROM 4 or the RAM 5 should be chip-enabled previously in the next address cycle. When the contents of the bit 7 are supplied to the part 3, either the ROM 4 or the RAM 5 to be chip- enabled is decided in the next address cycle.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprogram control system, and more specifically, to a method for highly efficiently utilizing a control storage device consisting of a ROM-RAM that stores a microprogram. The present invention relates to a preferred microprogram control method.

[Conventional technology]

Conventional microprogram control information processing equipment is
Programming is performed using a microinstruction set that specifies the basic operations of a processing device, which is stored in a control storage device, and the microinstructions are sequentially read from this storage device and executed to realize the operation of the processing device. do.

Conventionally, a control storage device is composed of a ROM and a RAM, and when the power is turned on, the ROM is read, a microprogram is read from an external storage device, etc. according to its contents, and after being loaded into the RAM, the microprogram is written from the contents of the first address of the RAM. The method of carrying out the
There are many publications such as Publication No. 34 and Japanese Unexamined Patent Publication No. 176843/1983.

- A method of switching between ROM and RAM in which the force control program is stored is also disclosed in JP-A-59-184949, JP-A-59-17641, and JP-A-60-173.
Publication No. 631, etc., are considered by the majority.

[Problem that the invention seeks to solve]

In the prior art described in each of the above-mentioned publications, RO
Switching between M and RAM is performed as follows. That is, R.O.
By switching between M and RAM using switches using contacts, and by connecting each part's control memory with connectors,
Conventional methods have been based on hardware contact switching, such as forcibly separating the conventional control memory and using external control memory.

Therefore, it is not possible to freely switch between ROM and RAM under microprogram control during system operation, and this is not particularly effective in terms of efficient use of the control storage unit for the limited microaddress space. It wasn't what it was supposed to be.

That is, in the conventional technology, hardware ROM/RAM
Since switching is performed, there is a problem in that once switching is performed, the ROM that has been disconnected and turned off cannot be operated again during system operation.

Furthermore, since the separated ROM cannot be used during system operation, there is a problem in that the storage device for controlling the ROM-RAM cannot be used efficiently.

The present invention was devised in view of the problems of the prior art described above, and it makes it possible to freely switch between ROM and RAM, which are control storage devices, during system operation.
The objective is to provide a microprogram control method that greatly improves AM usage efficiency.

[Means for solving problems]

The microprogram control method of the present invention is based on the ROM-RA
Microinstructions are sequentially read out from a control storage device consisting of M, according to the specifications of the microaddress register, and various information processing is performed. , it is characterized by switching between ROM and RAM from which microinstructions are read.

[Effect]

In a microprogram control type information processing device where the control storage section is composed of ROM/RAM, when the power is turned on, the program written in the ROM is executed.
A microprogram is loaded from an external storage medium etc. into RAM where nothing has been written yet, and the RAM
After loading is completed, the contents from the first address of the RAM are executed as a microprogram.

In the present invention, based on the series of initial microloading described above, a ROM and RAM switching instruction is included in the microinstruction, so that the ROM and RAM can be freely switched without bringing down the system while the microprogram is being executed. This is to improve the efficiency of ROM/RAM usage.

〔Example〕

The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the drawing, the contents of a microaddress register 1 are sequentially updated by a microaddress update circuit 2. The address signal output from the micro address register 1 is input to the ROM 4 on one side and R
Input to AM5. At this time, ROM4 or RAM5
Either one of them is chip-enabled by the output of the chip select section 3 and is in an operable state.

Therefore, ROM4 or RAM that is ready for operation
5, the microinstruction stored at the address is read out.

The read microinstruction is stored in the microinstruction register 6.
is stored in The microinstruction includes in advance a ROM/RAM switching bit 7 that indicates which of ROM4 and RAM5 should be chip-enabled in the next address cycle, and the contents of the ROM/RAM switching bit 7 are chip select. The information is input to section 3. This determines whether ROM4 or RAM5 will be chip-enabled in the next address cycle.

As shown in FIG. 1, the address area to which ROM 4 and RAM 5 are switched is microaddress area 8 common to both, and the above switching is not performed when reading other microaddress areas in RAM 5.

Figure 2 shows micro address register 1, R0M4 and R
It is a figure which shows the specific example of AM5. Micro address register 1 is composed of 14 bits of addresses O-13. The ROM 4 is constructed by arranging 32 kilobit elements with a depth of 4 and a data width of 8 bits up to a microinstruction width of 1 bit. RAM5 is 16 deep
It is constructed by arranging 64 kilobit elements with a data width of 4 bits and a microinstruction width of β bits. Here, for convenience, we will add 4 - to 4 to depth 16 of RAM5.
The ROM 4 is divided into areas A, B, C, and D as shown in the figure, and the entire area of the ROM 4 is defined as an area E.

The operation when the power is turned on will be briefly explained using the second drawing.

First, when the power is turned on, a microprogram loading program stored in advance in the ROM 4 (area E) is executed. As a result, the microprogram is loaded into areas B, C, and D of the RAM 4 from an external storage device (not shown). Next, control is transferred from the ROM 4 to the RAM 5 using the ROM/RAM switching bit 7 shown in FIG. 1, and the program in the RAM 5 loads a microprogram from an external storage device or the like into the area A of the RAM 5.

Normally, in the prior art, the ROM 4 used for initial loading of the microprogram is not used after all the microprograms are stored in the RAM 5.
Just make it work. However, now that the capacity of the ROM 4 has increased significantly, there is a great advantage in not only using the ROM 4 only for loading purposes, but also using the microprogram in the ROM 4 as part of the microprogram in the RAM 5 even during system operation. This is especially beneficial when the microaddress width is short and the available control storage capacity is limited.

FIG. 3 shows a specific example of the chip select section 3, and switching between the ROM 4 and the RAM 5 will be specifically explained according to the figure. In FIG. 3, ADH13 and ADH12 are the outputs (14 bits) of microaddress register 1.
Indicates the most significant bit and the bit one bit below the most significant bit,
ADH13-0 indicate all output bits. Also ADR1
(Negative) and (Positive) written after 3 etc. indicate negative logic and positive logic.

Then, ROM4 and RAM5 are set to 100 at the terminal (
It is assumed that it is enabled when negative logic L) is input.

In the chip select section 3 shown in FIG.
AM switching bit 7 is 0'', ADR12, 13 (negative)
are both "O" (both ADH12 and 13 (positive) are "1"
), ROM4 is chip-enabled and R
ADR12,1 when OM/RAM switching bit 7 is “1”
3 (negative) is 1", RAM5 is chip-enabled. In this way, ROM4 and RAM
The reason why M5 is not switched only by ROM/RAM switching bit 7 but by using the upper 2 bits/nodes ADR12 and 13 of microaddress register 1 is that RAM5 can output all bits of microaddress register 1 (14 bits/node ADR12, 13). )
This is because the ROM 4 uses only 12 bits excluding the upper two bits as an address signal.

That is, when the RAM 5 is executing the microprogram, the ROM/RAM switching bit 7 in the microinstruction register 6 is "1", and the terminal CB of the ROM 4, which shares the micro address O to 4kw, is set to "1". Enter “
By setting it to 0'', RC)M4 is disabled.

As a result, the microprogram in RAM5 is
Up to 6 kW are arbitrarily selected, read out to the microinstruction register 6, and processed.

Also, the R used for initial microprogram loading
By storing microprograms such as part of instructions and subroutines in the remaining area of OM4, RAM5
Four parts of ROM may be required during execution. In this case, the ROM/RAM switching bit 7, which is one bit of the microinstruction read and taken into the instruction register 6, is set to "0".
”, ROM is selected for microaddresses 0 to 4kw, and for microaddresses 4 to 16 -, since there is no control memory as ROM on the same microaddress, the microprogram in RAM 5 is taken over and selected. It happens.

As described above, when multiple control memories coexist in the same microaddress range, by providing a control memory switching bit in a part of the microinstruction, it is possible to arbitrarily control the Control memory can be switched, and control memory can be used efficiently.

Specifically, for example, a program in ROM4 is transferred to RAM5.
In addition to storing programs exclusively for loading into
It becomes possible to effectively utilize it as part of the microprogram in the RAM 5, and separate control memories arranged in the same microaddress area can be used while being switched during system operation. This allows, for example,
If a system has a limited microaddress width, is insufficient in capacity, and requires more microprogram area, it is possible to use ROM/R without expanding the microaddress width.
By providing the AM switching bit 7, the microaddress width is substantially expanded 1 and the capacity is increased, making it possible to realize highly efficient control storage. In addition, since all switching can be done under microprogram control,
This is an extremely useful method as it does not cause problems such as malfunctions or malfunctions due to poor contacts of the changeover switch.

In addition, in the embodiment described above, the ROM/RAM
Although only one switching bit is provided, the present invention is not limited to this, and a plurality of bits may be used.

This makes it possible to arbitrarily select many control memories located in the same address space during system operation by specifying the microprogram, making the system more effective.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to freely switch between ROM and RAM, which are storage devices for control, and the microprogram control greatly improves the utilization efficiency of ROM-RAM. method can be provided.

In other words, multiple control storage devices such as ROM/RAM placed in the same microaddress space within a limited microaddress range can be controlled without using contacts such as changeover switches, and once switched, system operation can be controlled. It is now possible to use the control memory such as ROM/RAM while switching it arbitrarily just by specifying it by the micro program, and the address space that can be used as the micro area increases. This is particularly effective as an efficient method of utilizing control memory when the bit width of the microaddress is short and the microaddress space is narrow.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a micro address register/ROM-R shown in FIG.
FIG. 3 is a block diagram showing a specific configuration of the AM. FIG. 3 is a block diagram showing a specific example of ROM/RAM switching by the chip select section shown in FIG. 1... Micro address register, 2... Micro address update circuit, 3... Chip select section, 4...
- Control ROM, 5... Control RAM, 6... Micro instruction register, 7... ROM/RAM switching bit. Agent Patent Attorney Tadashi Akimoto Figure 1 ■ A1.1□13-, -, -0 Figure 2 Figure 3

Claims (1)

[Claims] 1. In a microprogram control method in which microinstructions are sequentially read out from a control storage device consisting of ROM and RAM according to the specifications of a microaddress register, and various information processing is performed, RO
A microprogram control method characterized by including a switching instruction between M and RAM, and switching between ROM and RAM by a microinstruction.