JPS639267B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device for processing bit data of a display system used in a remote control device.

The bit data transmission format of the display system used in the remote control device is constructed as shown in FIG. In the transmission format shown in FIG. 1, codes 0, 1, 2, 3, .

Since the n-bit data shown in Figure 1 above is serially transmitted, the data is processed in units of bits or in units of 1 frame (n bits) using a microprocessor CPU (hereinafter referred to as μCPU). If you try to do this, the following drawbacks will occur: The μCPU mentioned above is usually manufactured for processing 8-16 bit data, so when n-bit data exceeds 8-16 bits as shown in Figure 1, it is difficult to perform parallel processing due to the performance of the CPU. It is not possible to do this. Furthermore, if serially transferred data is processed bit by bit, the processing time (overhead) will be too long and other processing will not be possible, resulting in a very poor efficiency.

The present invention was made in view of the above circumstances, and
It is an object of the present invention to provide a data processing device that divides data of a plurality of bits into a predetermined number of bits and processes them so as to be suitable for processing by a μCPU.

Hereinafter, the present invention will be explained in detail based on FIG. 2.

In FIG. 2, reference numeral 1 denotes a clock generating section which outputs a clock to the code detecting section 2. In FIG. Code detection section 2
detects one bit of data in synchronization with the clock from the clock generator 1, outputs a count signal to the bit counter 3, and increments the bit counter 3 by one. Further, the code detection unit 2 outputs the input bit data to the code determination unit 11. The bit counter 3 is
Setting values are stored according to the processing capacity of the CPU, and each time the count signal from the code detection section 2 is input, the count is performed. Then, this count value and a set value are compared, and when the count value becomes the same number as the set value, an overflow signal is output to the address counter 4 and the interrupt timing generator 5, respectively.
The address counter 4 increments by one in response to the overflow signal, and outputs this data to the interrupt timing generator 5 and the address data generator 6. The interrupt timing generator 4 outputs an interrupt signal to the interrupt controller 8 on the basis of the signals from the bit counter 3 and address counter 4. The address data creation section 6 creates an address for storing data based on the count value from the address counter 4, and outputs it to the data combination section 7. Sign determination unit 11
The bit data from the code detection unit 2 is “ON”.
The short pulse is set as "ON" and the long pulse is set as "OFF", and the results of this "ON" and "OFF" are converted into serial-parallel converter 1.
Output to 2. The "ON"/"OFF" signals from the serial-to-parallel conversion section 12 and the sign determination section 11 are converted into parallel signals. 13 is a memory and a serial-parallel converter 1
The converted data of step 2 is taken in and stored, and the stored data is output to the data combination section 7 in response to a signal from the address data creation section 6.
The data combination section 7 receives the word address from the address data creation section 6 and the data from the memory 13, and stores the "word address" and "data" in a combined state. Then, the “word address” and “data” are output to the bus 15 using a signal from the device selector 14 . This data coupling section 7 consists of a 16-bit memory,
For example, “address” is 6 bits and “data” is 10 bits.
It is now possible to decide in a timely manner, such as with a bit. If the μCPU 9 has an 8-bit processing capacity, the 16 bits are divided into the upper 8 bits and the lower 8 bits, and the device selector 14
Based on the signal, the upper 8 bits or lower 8 bits of data are output to the bus 15. if,
If μCPU9 is capable of 16-bit processing,
Naturally, there is no need to divide the data into two parts of 8 bits each. The interrupt control unit 8 includes an interrupt timing generation unit 5
Interrupts the μCPU 9 using an interrupt signal from the CPU. μCPU9 uses this interrupt to
Run the data input program stored in the . When the μCPU 9 has an 8-bit processing capacity, the data input program outputs a signal to the device selector 14 to output the upper 8 bits, and sends the upper 8 bits of the data coupling section 7 onto the bus 15. The data of the upper 8 bits is stored in the storage unit (hereinafter referred to as RAM) 16, and a signal is output again to cause the device selector 14 to output the lower 8 bits, and the lower 8 bits are transferred to the bus 1.
5 and output the lower 8 bit data to RAM1.
6.

The operation of the device configured as described above will be explained next.

Now, as shown in Figure 1, the 40-bit long/short code display data is divided into 10-bit units and sent to the μCPU 9.
shall be incorporated into the Bit counter 3 has
Set “10”. The code detection section 2 inputs one bit of bit data in synchronization with the clock. Then, the count signal is output to the bit counter to increment the bit counter 3 by one, and 1-bit data is output to the sign determination section 11 to determine whether it is "ON" or "OFF", and the result is serialized. - Output to the parallel converter 12. In this way, when the 10th bit of the display data is input to the code detection section 2, the bit counter 3 outputs an overflow signal to the address counter 4 and the interrupt timing generation section 5 since the number is the same as the set value. At the same time, set the count value of bit counter 3 to “0”.
Make it. The address counter 4 increments the counter by one and outputs the data to the interrupt timing generator 5 and the address data generator 6. The interrupt timing generator 5 receives the overflow signal and the signal from the address counter 4 and outputs the signal to the interrupt controller 8. The interrupt control unit 8 then issues an interrupt to the μCPU 9 to run the data input program.

On the other hand, the address data creation section 6 creates a 6-bit word address based on the data from the address counter 4 and outputs it to the data combination section 7, and also outputs a signal to the memory 13. The stored 10-bit display data is output to the data coupling section 7.

The data input program is device selector 1
4 outputs the signal twice, upper 8 bits and lower 8 bits.
The bit data is taken in and stored in the RAM 16. In this way, 10 bits of the 40 bits of display data shown in FIG.

In this explanation, the 40-bit data was divided into 10-bit units to make it a divisible number, but if you get a fraction, use the reset signal to turn it "ON"/"OFF" as shown in Figure 1. ``By setting the pulse to be longer than the code, the code determination unit 11 determines this pulse as the terminator, generates an interrupt, and performs the same process.

As described above, according to the present invention, display system bit data is divided into the required number of bit data and word addresses are assigned to the divided bit data. Development of a single program that allows the microprocessor to be used efficiently, and also allows the main computer to perform the microprocessor processing when multiple microprocessors are used to perform various controls. This has the advantage of being economically advantageous, such as making it possible to do so.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a transmission format of display system bit data of a remote control device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1...Clock generation section, 2...Sign detection section, 3
...bit counter, 4...address counter,
5... Interrupt timing creation section, 6... Address data creation section, 7... Data coupling section, 8... Interrupt control section, 9... CPU, 10... ROM, 11... Sign determination section, 12 ...Serial-parallel conversion section, 13...
Memory, 14...Device selector, 15...
CPU bus, 16... storage section.

Claims (1)

[Claims] 1. In a device that processes transmitted bit data using a microprocessor, there is a code detection section that detects the transmitted bit data, and a serial-parallel conversion that converts the bit data output from the code detection section into parallel data and stores it in memory. When the code detection section detects a preset number of bits, it outputs an interrupt signal, creates a word address for ranking the detected number of bits, and compares that word address with the number of bits set in advance. A data processing device comprising: means for storing data stored in a memory in a data coupling section; and means for storing data in the data coupling section in a storage section in response to the interrupt signal.