JPS6341075B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device, and more particularly to a display device that can flash.

As shown in FIG. 1, a conventional display device has a data memory 1 that stores n-digit numbers or character codes.
It consists of a segment decoder that converts data and codes from the data into segment outputs, a digit control circuit 3 that controls dynamic display, a segment drive device 4, and a digit drive device 5, and is sent from the central processing unit (CPU). Data input data
The data code corresponding to the digit output from the digit control circuit 3 is stored in the memory 1 and sent to the segment decoder 2.
In this method, the segment outputs are converted into segment outputs corresponding to numbers and characters, and sent one after another to the segment drive device 4, and dynamically displayed on the display unit 10.

To perform flashing with this conventional display device, as shown in Figure 2, the data of the digit to be flashed (in this case, the third digit) in data memory 1 is sent to the CPU in accordance with the flashing cycle, and the data is constantly turned on. It is necessary to send a code (FIG. 2a) and a blank code (FIG. 2b) to turn off the light to the display device. Flushing using this method has the disadvantage that flushing cannot be performed when the CPU is controlling other things, such as controlling a printer or in a hold state during direct memory access.

An object of the present invention is to provide a display device that can perform flashing without involving the CPU.

The present invention provides a display device that sequentially displays the contents of a data memory in which display information corresponding to each digit of a plurality of digits is written, digit by digit according to instructions from a digit control circuit. a flushing memory in which information is written, a flushing cycle generation circuit that generates a signal instructing the period during which flushing is to be performed, a signal connected to the first flushing memory and the flushing cycle generation circuit and instructing the period in which flushing is to be performed and a light-off timing control circuit that turns off only the display for the digits stored in the flashing memory only during the period when the flashing memory is activated, and controls the active period of the signal instructing the period to be flushed. This feature is characterized in that the flushing period of any specified digit is made variable by .

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 shows an embodiment of the invention. The digit control circuit 3, data memory 1, segment decoder 2, segment drive device 4, and digit drive device 5 have the same functions as conventional ones. It is provided with a flushing memory 7, a flashing cycle generation circuit 8 for determining a flushing cycle, and a light-off timing control circuit 6 for determining a light-off period, and the digit designated by a light-off signal DS is turned off for a certain period of time for flashing.

Specifically, a case will be explained by taking as an example a case where the second and fifth digits are flashed in a display device that dynamically displays a five-digit number. As shown in FIG. 4, during the period when the flushing signal FS, which is the output of the flashing cycle generation circuit 8, is at a low level, the light-off signal DS is at a low level, and as in normal dynamic lighting, the data corresponding to the digit output is output. are read out from the data memory 1 one after another, inputted to the segment decoder 2, converted into segment outputs corresponding to the data codes, and all digits are dynamically displayed one after another.

During the period when the flushing signal FS is at a high level, in order to turn off the digit specified by the flushing memory 7, a turn-off timing control circuit 6 as shown in FIG. In the logical product, the logical product of the 2nd and 5th digit becomes high level, and the light-off signal shown in Fig. 4 is generated.
DS occurs.

This turn-off signal DS controls the output of segment decoder 2, converts the low level period into a segment output corresponding to the data code and displays it, and displays the high level period (2 digits, 5 digits). eye)
forces the segment output to the OFF level and turns off the display. Then, the designated digit is periodically displayed for a certain period of time, and the remaining period is turned off to perform a flashing operation.

Another embodiment of the present invention will be described with reference to FIG.

This embodiment does not control display data, but
By controlling the digit output and turning off the specified digit, the above-mentioned turn-off signal DS is logically ANDed with the output of each digit, inhibiting the output of the specified digit and turning off the display, thereby performing a flashing operation. FIG. 7 shows the timing of this digit output control circuit, and the shaded areas are the digits that are off.

By providing the flushing memory, the flushing cycle generation circuit, and the light-off timing control circuit as described above, the present invention can perform flushing accurately and at any cycle without burdening the CPU.

When the display device of the present invention is used, since the display device controls flashing, the CPU can perform the flashing operation simply by giving a flashing command, so the CPU can concentrate on other processes, improving system efficiency. Significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional display device, and FIG. 2 is a diagram showing changes in data in a data memory when a flashing operation is performed in the conventional display device. FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 4 is a diagram showing the timing of a light-off signal, and FIG. 5 is a diagram showing a light-off timing control circuit. FIG. 6 is a diagram showing a circuit for controlling digit output in another embodiment of the present invention, and FIG. 7 is a timing diagram thereof. 1: data memory, 2: segment decoder,
3: Digit control circuit, 4: Segment drive device, 5:
Girder drive.

Claims (1)

[Claims] 1. In a display device that sequentially displays the contents of a data memory in which display information corresponding to each digit of a plurality of digits is written, digit by digit according to instructions from a digit control circuit, information indicating an arbitrary digit to be flushed is provided. The written flushing memory, a flushing cycle generation circuit that generates a signal instructing the period to be flushed, and a signal connected to the flushing memory and the first flushing cycle generation circuit and instructing the period to be flushed are activated. and an extinguishing timing control circuit that turns off only the display of the digits stored in the flashing memory during the period in which the flashing is to be performed, and by controlling the active period of the signal indicating the period in which the flashing is to be performed. A display device characterized in that the flashing cycle of any specified digit is made variable.