JPH02100747A - Data bus driving system for microprocessor - Google Patents

Abstract

PURPOSE:To display the performance of a high speed microprocessor even when an inexpensive, slow-speed memory is used by providing two data buses to the bus interface unit of the microprocessor. CONSTITUTION:This system is equipped with two data bus driver receivers 21 and 22 which read and write a system memory and a bus interface unit 20 having a control circuit 23 which operates the two data buses 21 and 22 at the same time and arbitrates the data buses 21 and 22. Consequently, data in a next cycle can be driven before the end of the current cycle when the microprocessor reads and writes the system memory continuously, so a margin of the cycle time of memory access is obtained and the performance of the high-speed microprocessor can be displayed even when a low-speed memory is used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data bus driving system for a microprocessor, and particularly relates to a data bus driving system for a microprocessor that operates when reading/writing a system memory.

[Conventional technology]

Conventionally, this type of microprocessor has a set of butty buses, and when the microprocessor executes a memory cycle, the data bus for the next memory cycle cannot be driven until the cycle is completed.

[Problem to be solved by the invention]

In the conventional microprocessor data bus drive method described above, when a microprocessor executes a memory cycle, there is only one set of data buses, so if the cycle is a read cycle, the instruction code or data read from memory is Until the data from the microprocessor is written to memory in the case of a write cycle, the microprocessor's bus interface unit must use the data bus only for that cycle; Memory read/write in microprocessor
The drawbacks were that a high-speed memory was required to reduce the write time, and a complicated circuit was required.

[Means to solve the problem]

The data bus driving system of the microprocessor of the present invention is a microprocessor bus interface system.
Two sets of data bus drivers/receivers that operate simultaneously only when reading/writing memory, and a control circuit that generates timing signals to alternately take these two sets of data internally and output them externally. Example 2 [Embodiment] The present invention will be described with reference to the drawings.
The figure shows an embodiment of the invention. Referring to FIG. 1, one embodiment of the present invention is a microprocessor database-driven system having two data bus interface units (IQ) and a system memory (IQ).
driver for two sets of data buses, luciver 2
1.22, and a control section circuit 23 for simultaneously operating the second set of data buses 21.22 and arbitrating between the two sets of data buses 21.22. There is.

To explain one embodiment of this in terms of a 16-bit microprocessor, the data bus driver/receiver 21 of the bus interface unit 1-20 has a microprocessor that handles the lower 16-bit processor of the memory. Data bus driver/receiver 22 operates only when the microprocessor reads/writes the upper 16 bits of memory.

The control circuit 23 connects the data bus driver/receiver 21 and 2
This circuit generates the control signals of 2 and various timing signals of the microprocessor.

FIG. 2 is a timing diagram when the microprocessor writes to the memory using the data bus driving method of this embodiment.5 In FIG. 2, the microprocessor outputs internal data, status, and address in one cycle period.

While this internal data memory address is continuous, it is alternately latched by the data bus driver/receiver 21 and 22 in FIG.

〔Effect of the invention〕

As explained above, the present invention provides two sets of data buses in the bus interface unit of a microprocessor, so that when the microprocessor continuously reads/writes the system memory, the next cycle is completed before the current cycle ends. Because data can be driven in cycles, there is more margin in the memory access cycle time.
This has the effect of bringing out the performance of a high-speed microprocessor even when using an inexpensive memory with relatively low speed.

FIG. 3 is a diagram showing the timing when writing .

10... Microprocessor, 2o... Old bus interface unit, 21.22... Data bus driver/receiver, 23... Control circuit.

Claims (1)

[Claims] A microprocessor that has a bus interface unit that has two sets of data buses, the microprocessor has a driver/receiver for the two sets of data buses that read/write system memory, and operates these two sets of data buses simultaneously. A data bus driving system for a microprocessor, characterized by having a bus interface unit equipped with a control circuit that arbitrates between these two sets.