JPS59202545A - Program controller - Google Patents

Abstract

PURPOSE:To decrease the display processing time by allowing the operation of an instruction decoder and a display decoder to be executed in parallel at each micro-state at the same time. CONSTITUTION:An instruction stored in an instruction register 29 and a display register 39 is decoded by an instruction decoder 30 and a control signal X1 is outputted to a conventional register 27 in the micro-state T3 when a data in the conventional register 27 in a microprocessor 21 is transferred to a display circuit 33 and this instruction is a display instruction displaying the information on a display panel 41. Then, this register 27 opens the gate by this control signal X1 and outputs the data to a data bus 26. On the other hand, a display instruction decoder 40 decodes the same instruction, outputs the control signal Y1 to a display register 34 in the micro-state T3, this register 34 inputs this control signal Y1 as a clock signal and stores the data on a data bus 26.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device, and particularly to a control system that includes a plurality of instruction registers and instruction decoders and processes reading, decoding, and execution of instructions in parallel.

The purpose of the present invention is to share a part of the information processing performed by a microprocessor with peripheral circuits, achieve faster processing by performing distributed processing, and reduce the number of connections between the microprocessor and peripheral circuits. The purpose of this invention is to provide a program control device 4.

A microcomputer system, which has traditionally been used in small information devices, consists of a microprocessor, an input/output interface controller, an external storage device, a display device that displays information, etc. has been done. Here, liquid crystal display panels are often used as display devices, but recently, improvements in liquid crystal manufacturing technology have led to the use of large-scale donot matrix liquid crystal display panels.

By using such a display panel, it has become possible to display various types of graph ink as well as characters, but as a result, the display circuit has become complicated, the contents controlled by the microprocessor have also become complicated, and the display commands have also become very large. This led to an increase in

For this reason, how to optimally design a control method for a display device has become an important element in system design, and conventionally the following two control methods have been considered.

FIG. 1 shows an example of a conventional program control device, in which 1 is a storage circuit for storing programs, 2 is an instruction register,
6 is an instruction decoder, 4 is an arithmetic circuit, 5 is a general-purpose register, 01 to Cn are control signals that control various internal circuits, and 6 is a data bus that connects the arithmetic circuit 4 and the general-purpose register 5 and outputs it to the outside. . A one-chip microprocessor 7 is configured as described above.

8 is an external display circuit, and 9 is a display panel such as a liquid crystal, which is driven by a drive signal group 10 output from the display circuit 8.

The display circuit 8 inputs the data bus 6 and further inputs display control signals D1 to Dn from the command decoder 6, and various controls necessary for display are directly performed by the microprocessor 7.

As described above, in this method, the instruction decoder 6 in the microprocessor 7 decodes all the display commands necessary for display and outputs the display control signal ~Dn, so the microprocessor 7 can directly control the display. However, if the number of display commands is increased to diversify display contents, the scale of the command decoder 6 will increase, and furthermore, the external display circuit 8 will be required.
There is a major drawback that the display control signals D1 to Dn increase.

FIG. 2 shows another example of a conventional program control device.
1 is a microprocessor having almost the same configuration as the microprocessor 7 previously shown in FIG. 1, and has an external data bus 12. Then, a switching signal A for switching between a command and data, and a write signal W for writing a command or data are output.

Reference numeral 16 denotes a display circuit, which includes an input register 14 for storing commands or data sent via the data bus 12, a command decoder 15 for decoding commands, a display RAM 16 for storing display information, and a drive circuit 17.

Reference numeral 18 denotes a display panel such as a liquid crystal, which is driven by a drive signal group 19 output from the drive circuit 17. Here, the display circuit 13 is controlled by a transfer command from the microprocessor sensor 1. That is, the microprocessor 11 reads and decodes the transfer command for controlling the display circuit 16. Next, when the decoded instruction is found to be a transfer instruction, a specific command is sent onto the data bus 12 and a write signal W is output at the same time.

lj<Water circuit 16 writes a command to input register 4 by executing the transfer command of microprocessor 11,
When it is determined that the information is a command based on the switching signal A,
The command decoder 15 decodes the command. Now, if this command specifies a write mode to transfer display data from the microprocessor 11 to the display RAM 16 in the display circuit 13, the display circuit 13 enters the write mode according to this command, and the information sent from the microprocessor 11 is is determined to be display data and written to the display RAM 16.

As described above, this method first uses the microprocessor 11.
reads, decodes, and executes the command and transfers the command,
Next, the display circuit 16 manually decodes and executes the command, which is the sequence of operations in which the tally mark 11 is executed.

That is, in this system, the microprocessor 11 and display circuit 13 are connected in addition to the data bus 12! (Honfishing has the advantage of being able to implement an interface with two signal lines, but since the operation order of the microprocessor 11 and display circuit 13 is performed in chronological order, it is larger than the conventional example shown in Fig. 1. The major drawback is that the execution rate is significantly reduced.

The present invention has been made to address the drawbacks shown in the above two conventional examples, and is capable of processing the control of the peripheral circuits of a microprocessor at high speed, and greatly reducing the number of connections with the peripheral circuits. It provides equipment.

Next, embodiments of the present invention will be described based on the drawings.

In FIG. 3, numeral 21 is a microprocessor which performs main control of the program control device of the present invention, and its configuration will be explained below.

22 is a timing generator that generates a reference clock signal 96CL and an address latch signal. , an instruction launch signal 〆1R1 and other timing signals necessary for control. 26 is a program counter that stores the address of the program being executed and outputs an address signal AD. 24 is an address launch circuit that inputs the address signal AD and temporarily stores address information using the address latch signal zAD; 25 inputs the output of the address launch circuit 24 as address information, and inputs and outputs programs or data to and from the data bus 26; This is a storage circuit composed of ROM and RAM. A general-purpose register 27 temporarily stores data, and is connected to the data bus 26 to input and output data. 28 is an arithmetic circuit that performs arithmetic operations between the general-purpose registers 27, and is connected to the data bus 26. Reference numeral 29 denotes an instruction register which inputs an instruction carried on the data bus 26 and temporarily stores it using an instruction latch signal R. 60 is an instruction decoder that receives the output of the instruction register 29 as input and decodes the instruction;
The control signal group X is outputted to the program counter 26, general-purpose register 27, arithmetic circuit 28, etc. according to the decoded command.

Reference numeral 61 is an input/output port which outputs data from the outside to the data bus 26, or temporarily stores data on the data bus 26 and outputs it to the outside.

Reference numeral 62 denotes an external operating member located outside the microprocessor 21, which transmits operating information into the microprocessor 21 via the input/output capotro 1.

Further, signal lines extending from the microprocessor 21 to the outside include a data bus 26, a reference clock signal zc, an instruction latch signal z1R1, and address information AD, ``'C'' if an external storage circuit is provided (not shown).

Next, provide a display circuit 3 outside the microprocessor 21.
The configuration of No. 3 will be explained.

A plurality of display registers 64 are connected to the data bus 26 to store data necessary for display.

65 is a display control circuit which inputs the output data of the display register 64, performs data processing, and outputs a display signal E. A display RAM 66 stores all pattern information to be displayed by inputting the display signal E, and outputs a group of display output signals F in a time-division manner. 67 is a display drive circuit;
A display output signal group F is input and a display drive signal group G is output. 68 is a display timing generator which inputs the reference clock signal 96cL and outputs a timing control signal H, which is input to the display control circuit 65.

In addition, the display timing generator 68 also outputs a display address signal I that determines the address of the display RAM 3B.
36.

A display command register 69 inputs command information on the data bus 26 and outputs an command launch signal.

The command is temporarily stored. Reference numeral 40 denotes a display command decoder, which decodes the command by inputting the output of the display command register 69, and outputs a display control signal group Y to the display register 648, display control circuit 65, etc. according to the command if it is a display command. control.

41 is a dondo matrix display panel using liquid crystal;
Display drive signal group G is input to display characters or graphics.

Next, the operation of this program control device will be explained with reference to the timing charts shown in FIGS. 3 and 4 shown above.

As shown in FIG. 4, the microprocessor 21 has four microstates T1 to T during one machine cycle, and these microstates are connected to a reference clock signal. , it changes by .

Here, the operations in microstates T1 and T2 are common to all instructions.

That is, in microstate T1, address signal AD is output from program counter 26 and input to address latch circuit 24. Since the address launch signal AD is generated at the timing shown in FIG. 4, the address latch circuit 24 stores the address signal AD and transmits the address information to the storage circuit 25.

Next, in microstate T2, as described in 1. Jin? circuit 2
5, the information according to the address information is transferred to the data bus 26.
Output to. Since the instruction latch signal n is generated at the timing shown in FIG. 4, the instruction register 29 stores the instruction information on the data bus 26 and transmits it to the instruction decoder 60.

Furthermore, the data bus 26 is connected to a display command register 69 in the display circuit 66, and also connects to a command latch signal 96+
Since + is also input as a clock signal to the display command register 69, the display command register 69 operates in exactly the same way as the command register 29 in the microprocessor 21, stores command information, and transmits it to the display command decoder 40.

Here, the instructions stored in the instruction register 29 and the display instruction register 9 transfer the data in the general-purpose register 27 in the microprocessor 21 to the display circuit 66, and the display panel 4
1, the instruction decoder 60 decodes the instruction and outputs the control signal x1 to the general-purpose register 27 in the microstate T3 as shown in FIG. Gate 4 is opened by signal X1 and data is output to data bus 26.

On the other hand, the display command decoder 40 decodes the same command and displays the fourth
As shown in the figure, the control signal Y1 is output to the display register 64 at ℃°C in the microstate T3, and the display register 64
inputs this control signal Y as a clock signal and stores the data on the data bus 26.

Next, in microstate T4, the display command decoder 40 outputs the control signal Y2° to the display control circuit 65 at the timing shown in FIG.
Output to M36. As a result, the display control circuit 65 converts the information in the display register 64 and outputs the display signal E according to the control signal Y2, and the display RAM 56 converts the information in the display register 64 to output the display signal E.
3, the display signal E is stored and the stored information is displayed on the display panel 41.

As described above, the instruction decoder 60 and the display instruction decoder 40
reads and decodes instructions in each microstate.
Since execution is performed simultaneously and control signals necessary for each block are output in parallel, the microprocessor and peripheral circuits operate as one, enabling parallel processing.

As a result, the processing speed of microprocessors including complex peripheral circuits has been increased, and when display commands are added due to the diversification of displays, the instruction decoder for the peripheral display circuits is often added. By simply doing this, you can create a system with a high degree of freedom.

Furthermore, the connection between the microprocessor 21 and the display circuit 61 requires only the data node 26, the reference clock signal 96c1, and the instruction launch signals X and 11, as shown in FIG. It is a system.

On the other hand, in the above embodiment, the operation of a general instruction has been described, but it is also possible to implement other special instructions.

In other words, the microprocessor 2
The instruction decoder 60 in the display circuit 1 decodes the operation instructions between the general-purpose registers 27 and performs necessary control.
A display command decoder 40 in the display RAM 66 decodes the display contents as a sweep command and performs necessary control on the display RAM 66.

In this way, instead of using multiple instruction decoders that decode the same instruction differently and operating them simultaneously, it becomes possible to perform distributed processing using a single microprocessor, significantly increasing the processing power of the entire system. is a person.

[Brief explanation of the drawing]

Figures 1 and 2 show a block diagram of a conventional program control device.
FIG. 3 is a block diagram showing the circuit configuration of the program control device of the present invention, and FIG. 4 is a timing chart showing the operation of the present invention. 21... Microprocessor, 22... Timing generator, 25... Memory circuit, 26... Data bus, 29... Instruction register, 60... ---Instruction decoder, 66 --- Display circuit, 39 --- Display command register, 40 --- Display command decoder, lc+, --- Reference clock signal, ylR ---・
... Command launch signal.

Claims (1)

[Claims] In a control device 1, which is composed of an arithmetic circuit that performs logical operations, a microprocessor having a memory circuit that stores programs, a display device, and a display circuit that displays information of the microprocessor on the display device. The microprocessor and the display circuit are each provided with an instruction decoder for decoding the instruction words of the program, and reading, decoding and execution of the instruction words to the two instruction decoders is carried out by a [Jll same timing signal]. A program control device characterized in that it is configured to perform parallel processing.