JPS6240567A - Interruption managing device - Google Patents

Abstract

PURPOSE:To manage efficiently an interruption by setting again an interruption level given to a peripheral device, to an optimum state by a software, in accordance with each system or its occasional state of the system. CONSTITUTION:To the tip of an interruption request line L, a peripheral device is connected. An interruption level setting register 5 is provided so as to correspond to the interruption request line L by one-to-one. The contents of the interruption level setting register 5 can be changed freely by changing the value of a setting register, for instance, so that it becomes a value which is different from an initial value, by a software, and also, setting an interruption level change flag. When a signal on the interruption request line L becomes on, the contents of the corresponding interruption level setting register 5 are outputted, and inputted to the corresponding code converting part 6. The output of each code converting part 6 is inputted to a priority encoder 2. The priority encoder 2 selects that of the largest value in output signals from plural code converting parts 6, and outputs a signal for showing the selected value as an interrupting signal. The interrupting signal is inputted to an M processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The interrupt level of a peripheral device is arbitrarily set and managed by software in accordance with various systems and the state of the system at the time.

[Industrial application field]

The present invention relates to an interrupt management device in which the interrupt level assigned to a peripheral device can be varied by software.

[Prior art and problems]

In conventional computer systems, latches are provided for peripheral devices, and the interrupt requests from each latch are input to a priority encoder, which selects the interrupt request with the highest interrupt level and processes the selected interrupt request. It outputs an interrupt signal with a corresponding value. In the conventional system, the interrupt level assigned to each peripheral device is fixed and cannot be changed according to the system state.

[Purpose of the invention]

The present invention is based on the above consideration, and an object of the present invention is to provide an interrupt management device in which the interrupt level for a peripheral device can be freely changed by software.

[Means to achieve the purpose]

Therefore, the interrupt management device of the present invention includes: an interrupt level output unit connected to one end of a plurality of interrupt request lines, and a plurality of interrupt level setting registers provided in one-to-one correspondence with each interrupt request line; a plurality of code conversion units provided in one-to-one correspondence to each interrupt level output unit and converting an m-bit code signal output from the corresponding interrupt level output unit into an n-bit code signal;
It has a bit signal line and the i-th signal line (where, i is 1.2
, ..., n) of the plurality of code converters.
output means for outputting a signal obtained by ORing the th signal, and means for writing a value specified by the microprocessor into an interrupt level setting register specified by the microprocessor; This device is characterized in that it is configured to output the contents of a corresponding interrupt level setting register when a signal on an interrupt request line is on.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In Figure 1,
2 is an interrupt management device, 2 is a priority encoder, 3 is an interrupt level output section, 4 is a register, 5 is an interrupt level setting register, 6 is a code conversion section, and L is an interrupt request line. A peripheral device is connected to the end of the interrupt request line L. 1 on interrupt request line L
An interrupt level setting register 5 is provided corresponding to pair 1. The contents of the interrupt level setting register 5 can be freely changed by software. When the signal on the interrupt request register 5 turns on (logical 1), the contents of the corresponding interrupt level setting register 5 are output and input to the corresponding code converter 6. The code converter 6 converts, for example, a 3-bit code into an 8-bit code. The output of each code converter 6 is input to the priority encoder 2. Priority encoder 2
selects the one with the largest value among the output signals from the plurality of code converters 6, and outputs a signal indicating the selected value as an interrupt signal. Interrupt signals are input to the microprocessor. For example, the microprocessor is 6800
0 (Motorola).

FIG. 2 is a diagram showing the flow of signals when an interrupt occurs. In the illustrated example, interrupt level setting register 5-1
The value of 3.5-2 is set to 2.5-3, and the value of 6.5-4 is set to 1.

In the illustrated example, the signal on the interrupt request line Ll is on, so the interrupt level output section 3-1 outputs "011", and the signal on the interrupt request signal line L3 is on, so the interrupt level output section 3-1 outputs "011". The unit 3-3 outputs rllOJ. The other interrupt level output units 3-2 and 3-4 output ro 00J. The code converter 6-1 is ro
11J to "00001000J, and the code converter 6-3 converts rl 10J to ro 1000000J. The code converters 6-2 and 6-4 convert ro o o
.

Outputs 0000J. Code converter 6-1 to 6-
The output signals of the first digit (i is 0, 1, . . . , 7) of 4 are ORed, and the ORed signals of the 0th to 7th digits are input to the priority encoder 2. In the illustrated example, the third of the input signals of the priority encoder 2
The digit and the sixth digit are "1", so the priority encoder 2 outputs rllOJ representing the numerical value 6.

This interrupt signal is sent to the microprocessor as described above. When the microprocessor is notified that there is an interrupt of interrupt level 6, it executes the corresponding interrupt processing program.

FIG. 3 is a diagram showing an example of a circuit for accessing the interrupt level setting register. In Figure 3, 7
8 indicates a data bus buffer, and 8 indicates a read/write control section. A unique address is assigned to each separate level setting register. For example, if a desired value is to be set in the interrupt level setting register 5-1, the desired value is placed on the data path, a unique address is placed on the address bus, and the write signal WR is set to a low level. Then, a desired value is set in the interrupt level setting register 5-1. It goes without saying that the microprocessor can read the value of the desired interrupt level setting register.

FIG. 4 shows the process for resetting the value of the interrupt level setting register to something different from the initial value. This process is performed by a program.

■ Change the value of the interrupt level setting register.

■ Turn on the interrupt level change flag.

FIG. 5 is a diagram showing the processing of the microprocessor when it receives an interrupt signal.

■ Check whether the interrupt level change flag is on. If it is off, process ``■'' is performed, and if it is on, process ``■'' is performed.

■ Perform processing as usual.

■ Perform processing associated with changes. For example, suppose that interrupt level 4 is initially assigned to peripheral device A, and then it is changed to interrupt level 5. Under this state, when the microprocessor receives a level 5 interrupt signal, it executes a program for processing whether the interrupt is from peripheral device A or not.

FIG. 6 is a diagram showing an example of use of the interrupt management device of the present invention. In FIG. 6, A to H indicate peripheral devices. FIG. 6(a) shows an example of use at the interrupt level during initial setting, and FIG. 6(bl) shows an example of use at the interrupt level when changing the system configuration.

By connecting a plurality of interrupt management devices of the present invention, more flexible system control can be achieved. As an example, FIG. 7 shows a usage example in which the interrupt management device of the present invention is arranged in a tree structure. In Figure 7, 9 to 11 are O
An R circuit is shown.

In the illustrated example, all peripheral devices under the interrupt management device 1-1 are finally given interrupt level 4 by the interrupt management device 1-3. Interrupt management device 1-2
is used by dividing it into two parts, and the peripheral devices under one 1-2-1 are finally given interrupt level 3 by the interrupt management device 1-3, and the peripheral devices under one 1-2-1 are given interrupt level 3, The peripheral devices under the control are finally given interrupt level 1 by the interrupt management device 1-3. Interrupt management device 1
-3 is given interrupt level 5 by the interrupt management device 1-3.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the interrupt level for peripheral devices can be reset to an optimal state depending on each system or the state of the system at the time.

[Brief explanation of drawings]

Figure 1 is a block diagram of one embodiment of the present invention, Figure 2 is a diagram showing the flow of signals when an interrupt occurs, and Figure 3 is an example of a circuit for accessing the interrupt level setting register. Figure 4 is a diagram showing the processing when resetting the value of the interrupt level setting register to something different from the initial value, and Figure 5 is a diagram showing the processing of the microprocessor when an interrupt signal is received. 6 is a diagram showing an example of use of the interrupt management device of the present invention, and FIG. 7 is a diagram showing an example of use when the interrupt management device of the present invention is arranged in a tree structure. l...Interrupt management device, 2...Priority encoder, 3...Interrupt level output unit, 4...Register, 5...Interrupt level setting register, 6...Code conversion unit, L. ...Interrupt request line.

Claims (1)

[Claims] An interrupt level output section connected to one end of each of the plurality of interrupt request lines, a plurality of interrupt level setting registers provided in one-to-one correspondence to each interrupt request line, and one-to-one correspondence provided to each interrupt level output section. a plurality of code converters configured to convert m-bit code signals outputted from corresponding interrupt level output units into n-bit code signals; and an n-bit signal line;
1, 2, ..., n), and an output means that outputs a signal obtained by ORing the i-th signals of the plurality of code converters, and an interrupt level setting register specified by the microprocessor. and means for writing a specified value, and the interrupt level output section is further configured to output the contents of the corresponding interrupt level setting register when the signal on the corresponding interrupt request line is on. An interrupt management device characterized by: