JPS639146A - Manufacture of photoelectric conversion device - Google Patents

Abstract

PURPOSE:To manufacture a photoelectric conversion device with simple processes and high yield at low cost by a method wherein, an insulating layer and a photoconductive semiconductor layer successively laminated are patterned. CONSTITUTION:In order to manufacture a photoelectric conversion device with an insulating layer 9 and a photoconductive semiconductor layer 10 provided on the insulating layer 9, said two layers 9, 10 successively laminated are patterned by means of at least a photoelectric converting part 3, a charge storage 4 storing the output from the photoelectric converting part 3 and a switch part 5 connected to the charge storage 4. For example, after forming lower layer electrode interconnections 6, 7, 8 on a glass substrate 1, the insulating layer 9 comprising silicon nitride, the photoconductive semiconductor layer 10 comprising amorphous silicon and an N<+>layer 15 are deposited. Next, after making a contact hole and forming upper layer electrode interconnections 12, 12', 13, 14, the N<+>layer 15, the photoconductive semiconductor layer 10 and the insulating layer 9 are partly removed so that respective elements may be independently isolated from one another.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a photoelectric conversion device, and in particular, at least a photoelectric conversion section, a charge storage section for accumulating the output of the photoelectric conversion section, and a charge storage section for accumulating the output of the photoelectric conversion section. The present invention relates to a method for manufacturing a photoelectric conversion device in which a switch part connected to a part has an insulating layer and a photoconductive semiconductor layer provided on the insulating layer.

[Prior Art] Conventionally, reading systems using a reduction optical system and a CCD type sensor have been used as reading systems for facsimiles, image scanners, etc., but in recent years, hydrogenated amorphous silicon (hereinafter referred to as a-Si:H Through the development of photoconductive semiconductor materials typified by It's amazing.

In particular, since the a-Si:H can be used not only as a photoelectric conversion material but also as a semiconductor material for field effect transistors, the photoconductive semiconductor layer of the photoelectric conversion section and the semiconductor layer of the signal processing section can be It has the advantage of being able to be formed simultaneously.

FIG. 16 is a partial vertical cross-sectional view of one configuration example of a conventional line sensor.

As shown in the figure, a wiring section 2. Photoelectric conversion section 3. Charge storage section 4. A switch section 5 is provided. On the substrate 1, there is a lower electrode wiring 6 of the wiring part 2. Lower electrode wiring of charge storage section 4 7. A lower layer electrode wiring 8 forming the gate electrode of the switch section 5 is formed, and these lower layer electrode wirings &16,7 are further formed.

An insulating layer 9 is formed on top of the insulating layer 8 . The insulating layer 9 of the switch section 5 includes a semiconductor layer (here L±, a-5i:H) 1
1 is formed on the substrate 1 of the photoelectric conversion unit 3, and a photoconductive semiconductor layer (here, a-3t:
H) 10 is formed. Note that here, the semiconductor layer 1
1 and the photoconductive semiconductor layer 10 are formed simultaneously.

A matrix wiring section is formed between the lower layer electrode wiring 6 and the upper layer electrode wiring 12 with an insulating layer interposed therebetween. Photoconductive semiconductor layer 10
and the semiconductor layer 11 are connected by an upper layer electrode wiring 13. The upper electrode wiring 13 is connected to pass over the insulating layer 9 of the charge storage section 4, and the upper electrode wiring 13, the insulating layer 9, and the lower electrode wiring 7 form a storage capacitor. The portion of the upper layer electrode wiring 13 connected to one end of the semiconductor layer 11 becomes a drain electrode, and the first layer electrode wiring 14 connected to the other end of the semiconductor layer 11 becomes a source electrode.

The above is the configuration when the photoelectric conversion section and the signal processing section are formed on the same substrate.
A semiconductor layer is formed only on the switch portion 5 and the insulating layer 9, and the photoconductive semiconductor layer 10 and the semiconductor layer 11 formed on the insulating layer 9 are formed by a manufacturing method such as a glow discharge method. Then, repatterning is performed by photolithography in the same way as the patterning of the upper layer electrode wiring and the lower layer electrode wiring.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional line sensor, the selectivity of etching between the semiconductor layer and the insulating layer is very poor in the photo-etching process of the semiconductor layer and the insulating layer, and the etching process of the semiconductor layer and the insulating layer is very poor. When etching is performed, the insulating layer is also etched, causing insulation defects, pinholes, etc., and significantly reducing yield.

In order to solve the above problems, a photoelectric conversion section is required.

It would be possible to form the charge storage section, switch section, wiring section, etc. in completely separate film formation and element fabrication process steps, but this would complicate the line sensor manufacturing process, increase the number of man-hours, and require them to be integrated on the same substrate. There was a problem in that the advantages of forming the wafer were not taken advantage of, and the cost increased.

An object of the present invention is to provide a method for manufacturing a photoelectric conversion device with simple steps, high yield, and low cost.

[Means for solving the problem] The above problem is such that at least the photoelectric conversion section, the charge storage section that stores the output of the photoelectric conversion section, and the switch section connected to the charge storage section, In a method for manufacturing a photoelectric conversion device having an insulating layer and a photoconductive semiconductor layer provided on the insulating layer, after the insulating layer and the photoconductive semiconductor layer are laminated in order, the insulating layer and the photoconductive semiconductor layer are laminated in order. This problem is solved by the method for manufacturing a photoelectric conversion device of the present invention, which comprises patterning a photoconductive semiconductor layer.

[Function] According to the method for manufacturing a photoelectric conversion device of the present invention, an insulating layer and a photoconductive semiconductor layer are laminated on at least the photoelectric conversion section, the charge storage section, and the switch section of the photoelectric conversion device. After the insulating layer and photoconductive semiconductor layer are formed, the insulating layer and the photoconductive semiconductor layer are patterned, eliminating the problem of etching selectivity between the insulating layer and the semiconductor layer, preventing deterioration of the insulating layer during manufacturing processes such as etching, and improving reliability. can improve sex. Furthermore, since the insulating layer and the leading conductive semiconductor layer can be formed at the same time in each component of the photoelectric conversion section, the manufacturing process can be simplified, and a compact photoelectric conversion mounting can be provided. Can be done.

In addition, in the second aspect of the present invention, when a photoelectric conversion device is provided with a wiring portion having a laminated structure of multiple layers, after laminating an insulating layer and a photoconductive semiconductor layer provided on this insulating layer, By patterning the layer and the photoconductive semiconductor layer to form the living room insulating layer, the living room insulating layer can be formed and etched in the same process as the photoelectric conversion section, the charge storage section, and the switch section.

[Example] Hereinafter, the present invention will be explained in detail using the drawings.

Note that a line sensor will be described as an example of a photoelectric conversion device manufactured according to the present invention.

In the following description, the same members as the line sensor shown in FIG. 16 are given the same numbers.

FIG. 1 is a partial vertical sectional view of an embodiment of a line sensor according to the present invention.

In FIG. 1, lower layer electrode wiring 6. Lower F3 electrode wiring of charge storage section 4 7. The lower layer electrode arrangement which is the gate electrode of the switch section 5 &! a8 is formed,
An insulating layer 9 is formed on these lower electrode wirings 6, 7.8 and on the substrate 1 between them. A photoconductive semiconductor layer 10 is formed on this insulating layer 9, and a wiring portion 2 is formed on the insulating layer 9.
A portion of the upper insulating layer 9 and the photoconductive semiconductor layer 1O are opened for connection. Upper layer electrode wirings 12, 12' and 13, 14 are formed on the photoconductive semiconductor layer lO,
The opening between the upper layer electrode wiring 12' and the upper layer electrode wiring 13 becomes a photoelectric conversion region of the photoelectric conversion section 3. Upper layer electrode wiring 1
3. Photoconductive semiconductor layer 10, insulating layer 9. Lower layer electrode wiring 7
forms a storage capacitor, and one end of the upper layer electrode wiring 13 on the switch section 5 side becomes a drain electrode. Upper layer electrode wiring 1
One end of 4 on the switch portion 5 side becomes a source electrode. Although not shown, the photoconductive semiconductor layer lO and the upper layer electrode wiring 1
In this embodiment, a doping layer is provided between the wiring portions 2.12' and 13.14, and ohmic contact is made. Photoelectric conversion section 3. Charge storage section 4. An insulating layer 9 is provided on each of the switch parts 5. Photoconductive semiconductor layer 10
are provided and formed in the same process.

In the wiring part 2, the lower layer electrode wiring 6 and the upper layer electrode wiring 1
In addition to the insulating layer 9, a photoconductive semiconductor layer 10 is provided between the lower electrode wiring 6 and the upper electrode wiring 12, as long as insulation is maintained between the lower electrode wiring 6 and the upper electrode wiring 12. The presence of layer 10 has no effect.

In the photoelectric conversion unit 3, the photoconductive semiconductor layer 10 is provided on the substrate 1 via the insulating layer 9, and this appears as a change in energy level at the interface between the photoconductive semiconductor 10 and the insulating layer 9. No changes occur that would impair the basic performance of photoconductive properties. In this case, it is also possible to provide an electrode between the substrate 1 and the insulating layer 9 of the photoelectric conversion section 3 to control and optimize the energy level at the interface of the photoconductive semiconductor layer 10.

In the charge storage section 4, the photoconductive semiconductor layer 10 provided on the insulating layer 9 gives ty to the charge storage capacity. This effect is due to the bias dependence of capacitance, and the capacitance changes due to band bending of the semiconductor layer at the insulating layer interface. However, in the charge/discharge operation of charges used in this embodiment, this bias dependence can be almost ignored by negatively biasing the electrode on the insulating layer 9 side.

Note that the film thickness of the photoconductive semiconductor layer 10 is set to a value that allows good photoelectric conversion characteristics of the photoelectric conversion section 3 and good switching characteristics of the switch section 5 to be obtained.

Next, a case will be described in which the switch section of the line sensor is configured by a matrix switch array.

FIG. 2 shows an equivalent circuit of a line sensor having a matrix switch array.

In the figure, St, S2, Φ..., SN (hereinafter referred to as SYI) are optical sensors indicating the photoelectric conversion unit 3. CI, C2,...φ, CM (hereinafter referred to as CYI) are storage capacitors indicating the charge storage section 4,
Let the photocurrent of YI be gM.

STI, Sr1, ---, STN (hereinafter,
5TYI) is a transfer switch, SR, for transferring the charge of storage capacitor CYI to load capacitor CXI.
I, SR2, . . . , 5RN (hereinafter referred to as 5RYI) are discharge switches that reset the charge of the storage capacitor CYI. In this example, the switch unit 5 includes a transfer switch 5TYI and a discharge switch 5RYl.

These optical sensor SYI, storage capacitor CYI.

The transfer switch 5TYI and the discharge switch 5RYI are arranged in a single row array and divided into NXM blocks. Transfer switches 5TY arranged in an array
I, the gate electrode of the discharge switch 5RYI is connected to the wiring section 2 formed in a matrix. Transfer switch 5
The gate electrode of TYI is commonly connected to the gate electrode of the transfer switch at the same rank in other blocks, and the gate electrode of the discharge switch 5RYI is connected to the gate electrode of the transfer switch at the next rank in each block. Connected in a circular manner.

The common lines (gate drive lines Gl, G2, . . . , GM) of the wiring section 2 formed in a matrix are driven by the gate drive section 21. - The force signal output is the lead line 23 (signal output line Di, D2).

..., DM) to the signal processing section 22.

FIG. 3 is a timing chart showing the operation of the line sensor.

Selection pulses (VGI) are sequentially applied to the gate drive lines (Gl, G2, . . . , GM) from the gate drive unit 21.

VO2, VO3, ---, VGN) are applied. First, when the gate drive line G1 is selected, the transfer switch STI is turned on, and the zero-order gate drive line G2 is selected, where the charge accumulated in the storage capacitor CI is transferred to the load capacitor CXI. and transfer switch ST2
is turned on, the charge accumulated in the storage capacitor C2 is transferred to the load capacitor Cx1, and at the same time, the charge in the storage container C1 is reset by the discharge switch SRI. Similarly, G3. G4.・・Φ.

GN is also selected and a read operation is performed. In the diagram, VCI, VO2, ---, VCN indicate changes in the potential of the storage capacitor CYI. These operations are performed for each block, and the signal output VXI of each block
, VX2. ---, VXM is the input D of the signal processing section 22
i, D2, . . . are sent to DIll, converted to unreal signals, and output.

FIG. 4 shows a perspective view of the line sensor.

In FIG. 4, reference numeral 1 denotes a substrate, and this substrate 1 includes a wiring section 2 formed in a matrix, a photoelectric conversion section 3, and a charge storage section 4 for accumulating output charges of the photoelectric conversion section 3. Transfer switches 5a arranged in an array to transfer the charges of the electric charge precision 4 to the signal processing IC 24, and discharge switches 5b arranged in an array to reset the charge storage section 4 are formed. Transfer switch 5a, discharge switch 5b
is divided into blocks into NXM, and transfer swift 5
The drain electrodes of a are connected to the corresponding charge storage sections 4, and the source electrodes are grouped into one for each block and connected to a load capacitor (not shown) and a signal processing IC 24. On the other hand, the gate electrodes of each block are connected to the wiring section 2 formed in a matrix so that the gate electrodes 8i & 1 of the same order in each block are commonly connected. A common electrode of this wiring section 2 is connected to the gate drive IC 25. The signal processing IC 24 is a switch array.

It is composed of a shift register, a buffer amplifier, etc., and reads out and resets the signal transferred to the lead line 23.

Further, this signal processing IC 24 is arranged near the center of the substrate 1 so that the wiring length of the lead line 23 is minimized. Note that a shield pattern (not shown) having a ground potential is arranged between the lead lines 23.

FIG. 5 shows a partial plan view of the line sensor.

In the same figure, 2 is a wiring part formed in a matrix, 3 is a wiring part formed in a matrix;
4 is a photoelectric conversion unit, 4 is a charge storage unit, 5a is a transfer switch, 5b is a discharge switch that resets the charge in the charge storage unit 4, and 23 is a signal processing IC for the signal output of the transfer switch.
A lead line 26 connected to the transfer switch 5a is a load capacitor for accumulating and reading out the charges transferred by the transfer switch 5a.

In this embodiment, the photoelectric conversion unit 3. A as a photoconductive semiconductor layer constituting the transfer switch 5a and the discharge switch 5b.
A -3i:H film is used, and a silicon nitride film (SiNH) formed by glow discharge is used as an insulating layer.

In FIG. 5, in order to avoid complexity, only the upper and lower two layers of electrode wiring are shown, and the photoconductive semiconductor layer and insulating layer are not shown. Photoelectric conversion section 3. Charge storage section 4. In addition to being formed in the transfer switch 5a and the discharge switch 5b, it is also formed between the upper layer electrode wiring and the substrate. Further, an n+ doped a-3iH layer is formed at the interface between the upper electrode wiring and the photoconductive semiconductor layer, and an ohmic junction is formed.

In addition, in the wiring pattern of the line sensor of this example, all signal paths output from each photoelectric conversion unit are wired so as not to intersect with other wiring, and crosstalk between each signal component and gate electrode wiring are avoided. This prevents induction noise from occurring.

FIG. 15 shows a partial plan view of the lead line 23 shown in FIG. 4.

In the figure, a ground pattern 28 is arranged between the lead lines 23 of adjacent blocks. This ground pattern 28 makes it possible to avoid crosstalk due to capacitive coupling between adjacent lead lines. Lead line 2
The line capacitance generated between the ground pattern 28 and the ground pattern 28 operates as part of a load capacitor. The difference in capacitance due to the difference in the wiring length of the lead wire of each block can be explained by adjusting the area of the load capacitor 26 to keep the effective capacitance of each block's load capacitor constant. This is the drawer terminal to be connected.

In the circuit configuration of this embodiment, the matrix wiring is performed on the gate electrode side of the switch section, and the source electrodes of the transfer switches in each block are combined into one wire, but the embodiment of the present invention is based on this circuit configuration. The present invention is not limited to this, and can be applied to various circuit configurations such as a configuration in which matrix wiring is performed on the source electrode side.

FIG. 6 is a partial vertical sectional view of FIG. 5, FIG. 6(a) is a sectional view along A-A', FIG. 6(b) is a sectional view along B-B',
FIG. 6(C) is a sectional view taken along line c-c'.

FIG. 6(a) shows a longitudinal cross-sectional view of the photoelectric conversion unit 3, in which 8' is a lower electrode wiring connected to the gate electrode of the transfer switch 5a, 9 is an insulating layer, 10 is a photoconductive semiconductor layer, 12 .1
3 is an upper layer electrode wiring. The incident light changes the conductivity of the a-3t:H photoconductive semiconductor layer 10, and changes the current flowing between the upper layer electrode wirings 12 and 13 facing each other in a comb shape.

FIG. 6(b) shows a longitudinal cross-sectional view of the charge storage section 4, which includes a lower electrode wiring 7, an insulating layer 9 formed on the lower electrode wiring 7, and a photoconductive semiconductor layer lO. dielectric and an upper layer electrode wiring 1 formed on the photoconductive semiconductor layer 10.
It consists of 3. The structure of this charge storage section 4 is a so-called M I S :1 y capacitor (Metal-Insu).
It has the same structure as the later-5 semiconductor. Although either positive or negative bias conditions can be used, stable capacitance and frequency characteristics can be obtained by always biasing the lower layer electrode wiring 7 in a negative direction.

FIG. 6(C) shows a longitudinal cross-sectional view of the transfer switch 5a and the discharge switch 5b. The semiconductor layer 10 is composed of a semiconductor layer 10, an upper layer electrode wiring 14 serving as a source electrode, and an upper layer electrode wiring 13 serving as a drain electrode. The gate insulating layer and photoconductive semiconductor layer of the discharge switch 5b are the same layer as the insulating layer 9 and the photoconductive semiconductor layer lO, and the source electrode is the same layer as the upper layer electrode wiring 1.
3. The gate electrode is the lower layer electrode wiring 8, and the drain electrode is the upper layer electrode wiring 14. The transfer switch 5a and the discharge switch 5b are thin film field effect transistors (TPT).
Configure.

As mentioned above, the upper layer electrode wirings 13, 14 . At the interface between the photoconductive semiconductor layer 10 and the photoconductive semiconductor layer 10, an n upper layer of a-5i:H is interposed to form an ohmic contact.

Note that the upper part of TPT is usually covered with a passivation film (Si
NH, S iOz , silicon-based, organic-based resin, etc.), but are not shown in FIG. 6(C).

As described above, in the line sensor according to the present invention, all of the constituent parts of the photoelectric conversion part, the accumulated charge part, the transfer switch, the discharge switch, and the wiring part formed in the matrix are made of a photoconductive semiconductor layer and an insulating layer. Since it has a laminated structure, each part can be formed simultaneously by the same process.

Next, a method for manufacturing a line sensor according to the present invention will be explained.

First, as a first example, a method for manufacturing the line sensor shown in FIG. 1 will be described.

FIGS. 7(a) to 7(e) are partial vertical cross-sectional views showing each manufacturing process of the line sensor of this embodiment.

First, as shown in Section 7IA(a), A was deposited on a cleaned glass substrate with good flatness by vacuum deposition.
1/Crho, deposited to a thickness of 1 gm.

A resist pattern is formed by photolithography and wet etching is performed to form a wiring portion 2 in a matrix. Charge storage section 4. Lower layer electrode wirings 6, 7.8 are formed in the transfer switch section which is the switch section 5.

Next, as shown in FIG. 7(b), an insulating layer 9 made of silicon nitride is deposited on the glass substrate by plasma CVD using 3i H4 gas and NH3 gas or N2 gas as raw materials by RF glow discharge. Deposit to a thickness of .3JLm. Subsequently, a photoconductive semiconductor layer 10, which is an amorphous silicon intrinsic layer, is formed using 5iHi gas as a raw material.
．． It is deposited to a thickness of 1 to 171 m. Next is 5iHa gas.

Using PH3 gas as a raw material, an n upper layer 15, which is an ohmic contact layer, is similarly deposited to a thickness of 1 gm.

Next, as shown in FIG. 7(C), a resist pattern is formed by photolithography, and dry etching is performed using CF4 gas to partially remove the n+ layer, photoconductive semiconductor layer, and insulating layer. A contact hole 16 is formed by removing it. At this time, selective etching of the n upper layer, the photoconductive semiconductor layer, and the insulating layer is not necessary.

Next, as shown in FIG. 7(d), A
Deposit l/Cr to a thickness of 1.0-1.54 m. After that, a resist pattern is formed by photolithography, and wet etching is performed to partially remove At/Cr.
and n upper layer is removed to form upper layer electrode wiring 12, 12', 1
Form 3.14. At this time, the lower layer electrode wire 6 and the upper layer electrode wire 12 of the wiring portion 2 formed in the matrix are electrically connected through the contact hole 16. Further, a gap of the photoelectric conversion section 3 and a channel of the transfer transistor section serving as the switch section 5 are formed.

Next, as shown in FIG. 7(e), a resist pattern is formed by photolithography, and dry etching is performed using CFa gas to partially remove the n upper layer, the photoconductive semiconductor layer, and the insulating layer. By removing the photoconductive semiconductor layer, each element, which has been electrically connected via the photoconductive semiconductor layer, is separated and electrically connected using only the necessary electrode wiring.

Next, a line sensor is manufactured by forming a passivation film (not shown) using silicon nitride, organic resin, or the like.

Next, a second embodiment of the present invention will be described.

FIG. 8 is a partial plan view showing a second embodiment of the line sensor according to the present invention. FIG. 10 is a partial vertical sectional view thereof.

The line sensor of this example irradiates light from the substrate l side,
This is a so-called lensless type photoelectric conversion device in which the photoelectric conversion section 3 directly reads reflected light from a document brought into contact with the photoelectric conversion section 3.

The photoelectric conversion section 3 is provided with a light shielding layer 17 that shields illumination light incident from the substrate side. Furthermore, an illumination window 27 for illuminating the original is provided.

9 is a partial vertical sectional view of FIG. 8, FIG. 9(a) is a sectional view taken along the line DD', and FIG. 9(b) is a sectional view taken along the line EE'.

As shown in FIG. 9(a), the illumination window 27 is formed by opening a part of the upper electrode wiring 12. As shown in FIG. This illumination window 27 may be formed by lower layer electrode wiring.

As shown in FIG. 9(b), the light shielding layer 17 is formed of lower layer electrode wiring. A negative bias voltage is normally applied to this light shielding layer 17, and the dark current is controlled so as to be sufficiently small.

The line sensor of the second embodiment is also shown in FIGS. 7(a) to (e).
The line senna is manufactured by the method of manufacturing the line senna of the first embodiment described above. However, in order to provide the light-shielding layer 17 in FIG. 10, when forming the lower electrodes 6, 7.8 shown in FIG. 7(a), the light-shielding layer 17 is also formed at the same time using the same material and the same processing method. .

Next, as a third embodiment of the present invention, a configuration example in which the pattern shapes of the lower layer electrode and the upper layer electrode of the first embodiment are exchanged will be described. The transfer transistor in the first embodiment is a so-called lower gate stagger type thin film transistor, and the present embodiment is a so called upper gate stagger type thin film transistor.

FIGS. 11(a) to 11(e) are partial longitudinal sectional views showing each manufacturing process of the line sensor of this embodiment. First, the cross-sectional configuration of this example will be explained using FIG. 11(e).

In FIG. 11(e), on the substrate 1 there is a lower layer electrode wiring 6. Lower electrode wiring of charge storage section 4 7. A lower electrode wiring 8 of the switch section 5 is formed, and an n-middle layer 15 serving as an ohmic contact layer is formed on these lower electrode wiring 6, 7.8. A photoconductive semiconductor layer 10 is formed between the n middle layer 151 and each lower electrode of the photoelectric conversion section 3 and the switch section 5, and furthermore, an insulating layer 9 and upper layer electrode wirings 12, 13, and 14 are laminated. ing. In the switch section 5, the upper layer electrode wire 14 becomes a gate electrode, the lower layer electrode wire 8 becomes a source electrode, and one end of the lower layer electrode wire 7 becomes a drain electrode.

Now, when the photoelectric conversion section 2 is irradiated with light, a current flows from the photoelectric conversion section 3 through the lower electrode wiring 7 to the charge storage section 4 due to the photoconductive effect, and charges are accumulated. The charge storage section 4 includes the lower electrode wiring 7. similar to the first embodiment. n middle layer 15. Photoconductive semiconductor layer 10° insulating layer 9. It is formed from the upper layer electrode 13. The accumulated charges are transferred to the photoconductive semiconductor layer lO and the lower electrode by turning on and off the upper layer electrode 14 of the transfer transistor section, which is the switch section 5, that is, the gate electrode, by signals sequentially sent from the wiring section 2 formed in the matrix. 8 and are sequentially transferred for reading.

Hereinafter, a method for manufacturing the above-mentioned line sensor will be explained.

First, as shown in FIG. 11(a), zero Al/Cr was deposited on a cleaned glass substrate with good flatness by vacuum deposition.
．． Deposit to a thickness of 1 pm. Furthermore, using the plasma CVD method, using 5IHa gas and PH3 gas as raw materials, the n-middle layer 1, which is an ohmic contact layer, is
5 is deposited in O1lBm. Thereafter, a resist pattern is formed by photolithography, and wet etching is performed to form a matrix of wiring portions 2.degree. charge storage portions 4. The lower layer electrode arrangement in the transfer switch part, which is the sweet and dry part! ! 6, 7, 8 and n middle layers 15 are formed.

Next, as shown in FIG. 11(b), on the glass substrate,
RF using SiH4 gas as raw material using plasma CVD method
A photoconductive semiconductor layer 10, which is an amorphous silicon intrinsic layer, is deposited to a thickness of 0.1 to 1 lumen by glow discharge. Subsequently, an insulating layer 9 made of silicon nitride was similarly formed using 5iHn gas and NH3 gas or N2 gas as raw materials.
Deposit to a thickness of 3.

Next, as shown in FIG. 11(C), a resist pattern is formed by photolithography, and dry etching is performed using CF4 gas to partially remove the insulating layer, photoconductive semiconductor layer, and upper n layer. Contact hole 1
form 6. At this time, an insulating layer, a photoconductive semiconductor layer, an n
No selective etching of the upper layer is required.

Next, as shown in FIG. 11(d), A I/Cr is deposited to a thickness of 1.0 to 2.04 m by a vacuum deposition method.

After that, a resist pattern is formed by photolithography, and wet etching is performed to partially remove A l /
Cr is removed to form upper layer electrodes 12, 13, and 14. At this time, the lower layer electrode wire 6 and the upper layer electrode wire 12 of the wiring portion 2 formed in the matrix are electrically connected through the contact hole 16. In the transfer transistor section which is the switch section 5, the upper layer electrode wiring 14 becomes a gate electrode.

Next, as shown in FIG. 11(e), a resist pattern is formed by photolithography, and dry etching is performed using CF4 gas to partially remove the insulating layer, photoconductive semiconductor layer, and n-layer. A line sensor is manufactured through one or more manufacturing steps in which each element, which has been electrically connected via a photoconductive semiconductor layer, is made independent and electrically connected only with necessary electrode wiring.

It is desirable that the electrical characteristic distribution of the photoelectric conversion section, charge storage section, and switch section of the line sensor arranged in an array is uniform for electrical driving. Since the thickness distribution is largely related to the characteristic distribution, it is desirable that the film thickness distribution be uniform.

In this example, the thicknesses of the insulating layer and the photoconductive semiconductor layer are determined at the time of film deposition (FIG. 11(b)), and the thicknesses of the insulating layer and the photoconductive semiconductor layer are determined during the subsequent fabrication process (FIG. 11(C)).

In (d) and (e)), the film thickness does not change. Therefore, if deposition conditions with good film thickness distribution are found, the uniformity of electrical property distribution will improve, and a line sensor with excellent uniformity can be easily produced.

Next, a fourth embodiment of the present invention will be described.

What about figure 12? FIG. 3 is a partial vertical cross-sectional view showing the configuration of the line sensor of the fS4 embodiment.

This example has a structure in which a light shielding layer 12' is provided on the upper layer of the photoelectric conversion unit 3 of the third example, and light is incident from the front side of the substrate element fabrication, and reflected light from the original brought into contact with the back side of the substrate is reflected. This is a so-called lensless type line sensor that is configured to read directly with a photoelectric conversion section. The illumination light illuminates the original from the surface side on which the substrate element is fabricated. At this time, the light shielding layer 12' prevents illumination light from entering the photoconductive semiconductor layer of the photoelectric conversion section 3, thereby preventing the generation of noise current.

The manufacturing process for manufacturing the line sensor of the fourth example is the same as that of the third example described above. However, the light shielding layer 12'
In order to provide this, when forming the upper layer electrode wirings 12, 13, and 14 shown in FIG. 11(d), the light shielding layer 12' is also formed at the same time using the same material and the same processing method.

As shown in FIG. 12, the light shielding layer 12' is provided above the photoelectric conversion section, and when a bias voltage (usually a negative voltage) is applied, the dark current can be controlled to be sufficiently small. have Note that the light shielding layer 12' may not be provided on the upper layer of the photoelectric conversion section 2, but may be provided on the unit housing section to which the tree line sensor is fixed to prevent irradiation light from entering the photoelectric conversion section. However, in this case, it is necessary to align the light shielding layer of the unin)C body with the main line sensor.

Generally, in a lensless type line sensor, it is necessary to place the original near the photoelectric conversion section 3, and in this embodiment, the original is placed on the back surface of the substrate 1. A glass substrate is generally used as the substrate 1, and the glass substrate has excellent optical properties and wear resistance, and can be used as a spacer for fixing the positional relationship between the photoelectric conversion unit 2 and the document.

That is, in this example, by appropriately designing the thickness of the substrate, the incident angle of illumination light, etc., a lensless type line sensor can be manufactured without requiring any special members. Furthermore, in this embodiment, since the photoelectric conversion section is provided on the substrate, there are only two vulgar interfaces of the document: the interface between the document surface and the substrate surface, and the interface between the substrate surface and the photoelectric conversion section. Since reflected light does not pass through,
Optical design becomes very easy.

In addition to the embodiments described above, at Kikomei, we are also able to manufacture devices with a structure that protects the photoconductive semiconductor layer, which is important for the characteristics of the photoelectric conversion section and the switch section, from damage and contamination during manufacturing. be.

Hereinafter, the configuration and manufacturing process will be explained using the fifth example and the sixth example.

In the fifth embodiment, an insulating layer made of silicon nitride is formed in place of the n-middle layer of the first embodiment, and then an opening is formed in the silicon nitride, and a photoconductive semiconductor layer and an upper electrode wiring are connected through this opening. The structure is such that electrical continuity is achieved.

FIGS. 13(a) to 13(e) are partial vertical cross-sectional views showing the manufacturing process of the line sensor.

First, as shown in FIG. 13(a), Al/Cre was deposited on a cleaned glass substrate with good flatness by vacuum deposition.
Deposit o, l JLm thick. 7. Wiring section 2 in which a resist pattern was formed by otolithography and a matrix was formed by wet etching. Charge storage section 4
．． Lower layer electrode wirings 6, 7.8 in the transfer switch section, which is the switch section 5, are formed.

Next, as shown in FIG. 13(b), on the glass substrate,
Using plasma CVD, an insulating layer 9a made of silicon nitride is deposited to a thickness of 0.3 m by RF glow radiation using SiH4 gas and NH3 gas or N2 gas as raw materials. Subsequently, a photoconductive semiconductor layer 1, which is also an amorphous silicon intrinsic layer, is formed using SiH4 gas as a raw material.
0 to a thickness of 0.1 to 1 lumen. Subsequently, an insulating layer 9b made of silicon nitride is deposited to a thickness of 0.3 degrees using S, iH4 gas, and NH3 gas or N2 gas as raw materials.

Next, as shown in FIG. 13(C), a resist pattern is formed by photolithography, dry etching is performed using CF4 gas, and an opening is formed in the silicon nitride 9b. As a raw material,
The n-middle layer 15, which is an ohmic contact layer, has a thickness of 0.1. lol
Deposit m.

Next, as shown in FIG. 13(d), a resist pattern is formed by photolithography, and dry etching is performed using CF4 gas to partially remove the n-layer, insulating layer, and photoconductive semiconductor layer. Contact hole 1
form 6. At this time, selective etching of the n+ layer, the insulating layer, and the photoconductive semiconductor layer is not necessary. Next, A1/Cr is deposited to a thickness of 1.0 to 1.5 m by a vacuum deposition method. After that, a resist pattern is formed by photolithography, and wet etching is performed to partially remove Al/
The Cr and n+ layers are removed to form upper layer electrode wirings 12, 13.
form 14. At this time, the lower layer electrode wire 6 and the upper layer electrode wire 12 of the wiring portion 2 formed in the matrix are electrically connected through the contact hole 16. Further, a gap of the photoelectric conversion section 3 and a channel of the transfer transistor section serving as the switch section 5 are formed.

Next, as shown in FIG. 13(e), a resist pattern is formed by photolithography, and dry etching is performed using CFa gas to partially remove the n-middle layer, photoconductive semiconductor layer, and insulating layer. , each element that had been electrically connected via a photoconductive semiconductor layer up to that point was made independent, and electrical connections were made using only necessary electrode wiring.

Next, a passivation film (not shown) is formed using silicon nitride, an organic resin, or the like, and a line sensor is manufactured.

It is desirable that the electrical characteristic distribution of the photoelectric conversion section and the switch section of the line sensor arranged in an array is uniform.
In the case of this example, the characteristic distribution only needs to be controlled by the film thickness distribution at the time of film formation.In other words, in this example, the gap part and channel part, which are important in the photoelectric conversion part and the switch part, are formed in the film formation process. It is protected by the formed insulating layer, and the shadow in the subsequent process! The configuration is such that it does not receive any Furthermore, since the films are formed continuously, it is possible to prevent the interface between the semiconductor layer and the insulating layer from being contaminated by impurities or the like. Furthermore, since the photoconductive semiconductor layer is already covered with an insulating layer, it has the advantage that the material for the final passivation film can be selected from a wide range.

Next, a sixth embodiment will be described.

The sixth embodiment has a structure in which a light-shielding layer 17 is provided on the lower layer of the photoelectric conversion unit 3 of the 55th embodiment as described above, and light is incident from the substrate side, and light from an original brought into contact with the surface of the photoelectric conversion unit is This is a so-called lensless type line sensor in which a photoelectric conversion section directly reads reflected light.

FIG. 14 is a partial vertical sectional view of one configuration example of the sixth embodiment.

As shown in FIG. 14, illumination light enters the document from the substrate side.

The manufacturing process for producing the sixth embodiment is the same as that of the fifth embodiment described above. However, the light shielding layer 17 is
When forming the lower electrode wirings 6.7.8 shown in , they are formed simultaneously using the same material and the same processing method.

In this example, the second example, and the fourth example, the incident light to the photoelectric conversion section is configured to enter from above, so that the upper side interface of the photoconductive semiconductor layer in the gap part of the photoelectric conversion section is particularly used. In this example, the interface of the gap part is formed with a continuous groove film, and in the subsequent steps, it is protected by an insulating layer, so that, for example, etching is not necessary. Compared to the case where the gap portion is formed using a process, it is less susceptible to contamination by impurities and stable characteristics can be obtained.

Also, similar to the fifth embodiment described above, since the photoconductive semiconductor layer is already covered with an insulating layer, it has the advantage that the material for the final passivation film can be selected from a wide range. .

[Effects of the Invention] As described above in detail, according to the method for manufacturing a photoelectric conversion device according to the present invention, an insulating layer and an insulating layer are provided in at least the photoelectric conversion section, the charge storage section, and the switch section of the photoelectric conversion device. After laminating the photoconductive semiconductor layer provided on the photoconductive semiconductor layer, the insulating layer and the photoconductive semiconductor layer are subjected to a one-to-two process to prevent deterioration of the insulating layer during the manufacturing process such as the etching process. This can significantly reduce short-circuit defects, capacitance variations, insulation deterioration at electrode wiring intersections, etc. in charge storage areas and upper and lower wiring intersections, etc.
Reliability can be improved.

In addition, since each component of the photoelectric conversion device can be formed simultaneously, manufacturing processes such as film formation and device fabrication processes can be simplified.Furthermore, since the basic configuration of each component is the same, integration is possible. It is suitable for this purpose, and it is possible to provide a compact photoelectric conversion device. As a result, it is possible to reduce costs and provide a photoelectric conversion device with a high degree of freedom in setting.

In the present invention, when providing a wiring portion having a multilayer structure in a photoelectric conversion device, after forming an insulating layer and a photoconductive semiconductor layer provided on this insulating layer, By patterning a photoconductive semiconductor and using it as the living room insulating layer, the living room insulating layer can be formed in the same process as the process of forming the photoelectric conversion section, the charge storage section, and the switch section.

[Brief explanation of the drawing]

FIG. 1 is a partial vertical sectional view of an embodiment of a line sensor according to the present invention. FIG. 2 shows an equivalent circuit of a line sensor having a matrix switch array. FIG. 3 is a timing chart showing the operation of the line sensor. FIG. 4 shows a perspective view of the line sensor. FIG. 5 shows a partial plan view of the line sensor. FIG. 6 is a partial longitudinal sectional view of FIG. 5. FIG. 7 is a partial vertical sectional view showing each manufacturing process of the line sensor. FIG. 8 is a partial plan view showing a second embodiment of the line sensor according to the present invention. FIG. 9 is a partial vertical sectional view of FIG. 8. FIG. 10 is a partial vertical sectional view of the partial plan view shown in FIG. 8. FIGS. 11(a) to 11(e) are partial vertical cross-sectional views showing each manufacturing process of the line sensor. FIG. 12 is a partial longitudinal sectional view showing the configuration of the line sensor. FIGS. 13(a) to 13(e) are partial vertical cross-sectional views showing the manufacturing process of the line sensor. FIG. 14 is a partial vertical sectional view of one configuration example of the sixth embodiment. FIG. 15 shows a partial plan view of the lead line 23 shown in FIG. 4. FIG. 16 is a partial vertical cross-sectional view of one configuration example of a conventional line sensor. 1.φ...Substrate 2e...Wiring section 3...Photoelectric conversion section 4...Charge storage section 5...Switch section 6.7.8... Lower layer electrode wiring 9...Φ・Insulating layer 10...Fist・Light conductive semiconductor layer 12.12', 13.14... Upper layer electrode wiring agent Patent attorney Minoru Yamashita Child 3 diagram VS2 -m - vC2VRi-anti-vCNvl? VXI ←J-ゝ-- Fig. 6 (C-n Fig. 7 Fig. 9 Fig. 10 Fig. 12 Fig. 11 Fig. 13

Claims (3)

[Claims] (1) At least a photoelectric conversion section, a charge storage section that accumulates the output of this photoelectric conversion section, and a switch section connected to this charge storage section are formed by an insulating layer and a photoconductive layer provided on this insulating layer. A method for manufacturing a photoelectric conversion device having a semiconductor layer, characterized in that after the insulating layer and the photoconductive semiconductor layer are laminated in order, the insulating layer and the photoconductive semiconductor layer are patterned. A method for manufacturing a photoelectric conversion device. (2) In a photoelectric conversion device in which a wiring section having an insulating layer and a photoconductive semiconductor layer provided on the insulating layer is provided between an upper layer wiring and a lower layer wiring, the insulating layer and the photoconductive semiconductor layer are provided. 2. The method of manufacturing a photoelectric conversion device according to claim 1, wherein the insulating layer and the photoconductive semiconductor layer are patterned after the photoconductive semiconductor layers are sequentially laminated. (3) The method for manufacturing a photoelectric conversion device according to claim 1, wherein the photoconductive semiconductor layer is hydrogenated amorphous silicon.