JPS6389954A - Memory control system - Google Patents

Abstract

PURPOSE:To shorten the accessing time of a memory to be accessed at the next time in a read and a write operations, by latching an address and/or data accessed at this time. CONSTITUTION:After first time of accessing, the address from a system bus 8 is compared with values loaded on counters 2A and 2B by a comparator 3. When coincidence is obtained between them, in other words, when the next address is read, an inverted XACK is returned immediately to the system bus 8, and a data latched at a data latch 6 in advance is outputted. After a state goes to a command inactive state, a pre-read cycle by a page mode is executed in the inside of a memory system, and the data corresponding to the address counted up by one is latched at the data latch 6. When the address is varied in order like a DMA cycle, a regular accessing time is necessary only for a first cycle, but after that, fast cycle is applied, thereby, the accessing time can be remarkably shortened.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a memory control method, and in particular to shortening the access time of the next accessed memory in read and write operations by latching the currently accessed address and/or data. This paper relates to a memory control method that makes it possible.

BACKGROUND OF THE INVENTION In recent years, with the increase in memory integration, the usage (capacity) of memory in image processing systems and the like has been on the rise. For example, as shown in FIG. 3, the image memory, frame buffer, and page buffer each have a capacity of one page or more in many cases.

Image data edited and processed in the system memory is transferred to a page buffer and a frame buffer by a direct memory access (DMA) controller or the like, and printed or displayed.

The above transfer is executed via the system bus, so the CP
In order to increase the efficiency of U, it is desirable to complete the process in as short a time as possible. One of the major factors that determines transfer time is memory access time.

In conventional memory control methods, in the case of reading, a control signal is generated to the memory after a memory read request occurs, so there is a problem that the same cycle time is required for each cycle. . In the case of writing, after the Write I command is given, the signals necessary for memory writing are generated, and after the writing is completed, a transfer end signal (XAC) is sent to the system bus.
K), a similar problem occurred.

To shorten the access time, it is possible to use a high-speed memory device, but this creates another problem: high cost.

Purpose The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional memory control methods, and to perform read/write operations only when accessing memory according to a certain set of rules. An object of the present invention is to provide a memory control method that can shorten access time in operation.

Configuration The above-mentioned object of the present invention is to provide a control system for a memory device connected to a system bus, in which read/write addresses and read/write data are latched in response to memory read/write commands from the system bus. This is achieved using a unique memory control method.

Hereinafter, the configuration of the present invention will be explained in more detail based on examples.

FIG. 1 is a memory read control block diagram showing one embodiment of the present invention. In the figure, 1 is an address buffer, 2
A is an upper bit counter, 2B is an F-order pi 1-counter, 3 is an address comparator (hereinafter, !11- is referred to as a "comparator"), 4 is a timing generator, 5
is a memory, 6 is a data latch, 7 is a multiplexer, and 8 is a system bus.

-4- The counters 2A and 2B are for upping the next memory address from karan 1, and the comparator 3 is for checking whether the address from the system bus 8 matches the address indicated by the counter. It has the function of checking and checking. Furthermore, the timing generator 4 generates signals necessary for controlling the memory 5 and generates clocks for the counters 2A and 2I3.

It has functions such as data latch 1 control and XACK generation.

First, an outline of the operation of this embodiment will be explained using FIG. 4. FIG. 4(a) shows the prior art, and FIG. 4(b) is a timing chart of this embodiment. The operation of this embodiment is to use the idle time of the read cycle that always occurs due to the cycle time of the DMA controller, system bus constraints, etc. in the DMA cycle, and read and latch the next address in the DRAM page mode during this time. Then, when a memory read of the next address occurs, the system is immediately notified of the end of reading, and the next address is read again in page mode. This operation is repeated thereafter to achieve high-speed memory transfer.

The details of the operation will be explained below based on FIGS. 2(,) to (c).

(1) Random read (see FIG. 2(a)): This is the timing when accessing an address completely different from the first address or the previous address (n)+1. A normal memory read cycle is executed for the system bus. Naturally, the access time will be the same as before.

That is, first, the address from the system bus 8 is loaded into the counters 2A, 2B, and then the address is input to the memory 5 via the multiplexer 7. At the end of the transfer, the counters 2Δ and 2B are incremented by "1" by the XACK.

After the command becomes inactive, a page mode read-ahead cycle is executed inside the memory system, and data corresponding to the address counted up by 1'' is latched into the data latch 6.

(2) Fast cycle (Figure 2 (b): After the first access, the address from the system bus 8 and the counter 2
The comparator 3 compares the values loaded in A and 2B, and if they match, that is, if the next address is to be read, the XACK is immediately returned to the system bus and the data latch 6 is loaded in advance. The latched data is output.

After the command becomes inactive, a read-ahead cycle in page mode is executed inside the memory system, and 1
11 II The point that the data corresponding to the address whose count has been increased is latched in the data latch 6 is similar to (1).

When addresses change sequentially, such as in a DMA cycle, normal access time is required only in the first cycle, but after that, fast cycles are used, so access time is significantly shortened, and transfer time is also shortened. .

(3) Page switching mode (see Figure 2 (c)): DR
When the page in AM changes, that is.

This timing is applied when all lower addresses become "1".

RAS becomes "H" once, and the next page is accessed. It is also applied when the RAS pulse width reaches the Max value.

According to this embodiment, there is an effect that the access time for memory read in DMA transfer is significantly shortened.

FIG. 5 is a memory write control block diagram showing another embodiment of the present invention. In the figure, symbols 1゜5.7.8 indicate the same components as shown in Figure 1, 2 is an address latch, 4A is a timing generator, 6A is an output data latch, 6B is a manual data latch, and 9 is a manual data latch. A data transceiver is shown.

The timing generator 4A has functions such as generating signals necessary for controlling the memory 5 and generating the XACK.

First, an outline of the operation of this embodiment will be explained using FIG. 6. FIG. 6(a) shows the prior art, and FIG. 6(b) shows the timing chart 1- of this embodiment. The operation of this embodiment is such that in a memory write cycle, the CPU
Alternatively, first, send back a transfer end signal using the empty time of the write cycle that always occurs due to the cycle time of DMA controller 1 to roller, system bus constraints, etc.
A write cycle is executed within the memory system during the above-mentioned free time, independently of the system bus.

That is, when a command is input to the system bus, the address and data are internally latched, and the X
Outputs ACK. A write cycle is executed within the memory system by using the time until CI)U detects the XACK and the time for internal processing of CI)U.

The details of the above operation will be explained below based on FIG. 7.

(1) Write cycle (refer to the phase in Figure 7) When a write command is input from the system bus 8, the write address/data is converted into an address within the memory by ANDing the RAS inactive and the write command. Latch into latch 2/input data latch 6B.

At the same time, the timing generator 4A is activated. After startup, the XACK is immediately output to the system bus 8. Inside the memory, then R
Signals such as AS, CAS, and WE are output from the timing generator 4A, and a write cycle is executed.

(2) When the next cycle occurs while an internal cycle is being executed (see phase ① b in Figure 7): When using a high-speed DMA controller, etc., the next command may occur while an internal cycle is being executed. .

In other words, the command becomes active when RAS is active, and in this embodiment, the command becomes active when RAS is active.
Since the S inactive and the command active are ANDed and latched and activated, it simply waits until the RAS becomes inactive, that is, until the end of the internal cycle.

For the system, the XACK is delayed by the time the RAS is inactive. After RAS inactivity,
Since the next cycle is executed immediately, there is no idle time in the memory, making it efficient.

According to this embodiment, the access time at the time of memory write is shortened, which has the effect of improving the usage efficiency of the memory system.

It goes without saying that the present invention should not be limited to the above embodiments.

Effects As described above, according to the present invention, in a control method for a memory device connected to a system bus, read/write addresses, read/write I Since the structure is configured to latch data, it has the remarkable effect of realizing a memory control system that can shorten the access time in read/write operations only when accessing the memory according to a certain predetermined rule.

[Brief explanation of the drawing]

FIG. 1 is a memory read control block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing details of the operation of the embodiment, FIG. 3 is a diagram showing an example of the configuration of an image processing system, and FIG. 4 is a timing chart showing a comparison between the prior art and this embodiment, FIG. 5 is a memory write control block diagram showing another embodiment of the present invention, and FIG. 6 is a timing chart showing a comparison between the prior art and this embodiment. FIG. 7 is a timing chart showing details of the operation of the embodiment. 1 near address buffer, 2 near address latch, 2A:"
] digit bit counter, 2B = lower bit counter, 3:
Comparator, 4: Timing generator, 5: Memory, 6: Data latch, 6A: Output data latch, 6B
Two-person data latch, 7: multiplexer, 8 system bus, 9: data transceiver. Procedural amendment (voluntary) November 5, 1985 61 Patent 235564 Showa
Year Application No. 2, Name of the invention Memory control method 3, Relationship with the case of the person making the amendment Patent applicant 4, attorney 5°C Number of inventions increased by amendment L16f Subject of amendment 11JJ [1F (71r. ,.-14.. (1) The description in the "Detailed Description of the Invention" column is amended as follows: 1) Page 3, line 10, page 5, line 6, page 6, line 12. eye. Page 7, line 4, Page 8, line 15, Page 9, line 9, 10
rXAcKJ in line 3, page 10, line 20,
Correct with rXACKJ. 2) Page 8, line 1, line 2, page 9, line 17, line 10
Page 4th line, 12th line, 14th line, 16th line, 1st page
rRAsJ on the 9th line and 20th line is corrected to rRASJ. 3) Correct rcAsJ on the 4th line of page 10 to rCASJ. 4) Correct rWEJ on the 4th line of page 0 to "rWE".

Claims (3)

[Claims] (1) A memory control method for a memory device connected to a system bus, characterized in that read/write addresses and read/write data are latched in response to memory read/write commands from the system bus. method. (2) The memory control system according to claim 1, characterized in that data at a next address is pre-read and latched at the end of a memory read cycle from the system bus. (3) During a memory write cycle, the write address/write data is latched, a transfer end signal is immediately returned to the system bus, and the write cycle is executed within the memory. The memory control method described in item 1.