JPS638838A - Logic verifying system - Google Patents

Abstract

PURPOSE:To automatize setting of a status value to a logical memory and reduce the man-hour for logic verification of a logic circuit including the memory by providing a logical memory defining means. CONSTITUTION:A logical memory definition description (a) from an input means 1 and physical memory information (c) in the definition description (a) from a design data base A are inputted to a logical memory defining means 2 to generate logical memory definition information (d) indicating correspondence between the logical memory and a physical memory. Logical memory definition information (d) is referred to input a status value (e) to a status value setting means 3 from one status value file B corresponding to the capacity of the logical memory, and the means 3 sets a status value of the logical memory. A logical memory (f) whose status value is already set and another circuit information, which is required for operation execution of the logical memory (f), from the design data base A are inputted to a simulation model generating means 4 to generate a simulation model (h). The simulation model (h) is inputted to a simulation means 5 to simulate the logic.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a logic system that verifies whether design result data (hereinafter referred to as design data) for a logic circuit including a memory is correct by simulating the logic circuit. Regarding verification method.

[Conventional technology]

In this type of logic verification method, the state values of programs, firmware, etc. that are to be stored after completion in memory are apparently stored, the state values are read out, deciphering is simulated, and the state values are simulated. Verify whether the logic circuit design is correct or not based on the results.

When actually configuring it as a device, for example, if a plurality of commercially available memory chips (physical memory chips) are combined into one program memory (logical memory chip), the design database contains physical memory as a unit. On the other hand, state values such as firmware are allocated to one logical memory.

For this reason, in the past, it was necessary to create a state value file for each physical memory in the design database prior to logical simulation of the memory. Then, state values are set in the physical memory from the state value file in units of physical memory.

[Problem that the invention seeks to solve]

The conventional logic verification method described above has the disadvantage that it requires a large number of man-hours to create state value files as many as the number of physical memories and to set state values for each physical memory. Furthermore, since there are multiple status value files, there is a drawback that troubles are likely to occur in terms of file management.

[Means for solving problems]

The logic verification method of this invention groups memory chips (hereinafter referred to as physical memory) in a logic circuit design database, and uses the memory chips (hereinafter referred to as logical A means for manually creating a logical memory definition description that defines a memory (referred to as memory), a means for creating logical memory definition information from the logical memory definition description and information about the physical memory of the definition description in a design database, means for reading a required state value from a state value file with reference to memory definition information and setting the state value in the logical memory;
means for creating a simulation model from the remaining circuit information required for the operation of the state value setting means logical memory and the logical memory obtained from the design database; means for logically simulating the simulation model; and means for logically simulating the simulation model; and means for outputting.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the logic verification method of the present invention.

A logical memory definition description a, such as the number of words and bits of the logical memory, the physical memory to be used, and its address correspondence, is input from the outside through the input means 1.

The logical memory definition means 2 obtains the logical memory definition description a from the manual means l and the physical memory information C in the definition description a from the design database A (its physical memory characteristics, that is, whether it is a negative polarity memory or not, is a negative polarity address). (such as whether the logical memory is a physical memory or not) and creates logical memory definition information d indicating the correspondence between the logical memory and the physical memory. Status value setting means 3
refers to the logical memory definition information d, inputs the state value e from one state value file B corresponding to the size of the logical memory, and sets the state value of the logical memory.

The simulation model creation means 4 inputs the logic memory f for which state values have been set, the design database A, and other circuit information flags necessary for executing the operation of the logic memory f, and creates a simulation model h. The simulation means 5 inputs the simulation model h and performs a logic simulation, and the output means 6 outputs the logic simulation result i to the outside.

〔Effect of the invention〕

As explained above, by providing a logical memory definition means, the present invention automatically sets state values for the logic memory, reduces the number of steps required for logic verification of logic circuits including the memory, and manages state value files. This has the effect of making it easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the logic verification method of the present invention.

Claims (1)

[Claims] (1) A design database that stores design results for logic circuits including memory chips (hereinafter referred to as physical memory), and a memory that is designed with multiple of the above physical memories as one memory space (hereinafter referred to as logical memory) ), a means for inputting a logical memory definition description indicating the correspondence between a file storing state values to be stored in the above logical memory and the physical memory, and a means for inputting data regarding the physical memory of the input logical memory definition description. Means for reading from a design database to create logical memory definition information indicating the correspondence between logical memory and physical memory, and reading the above-mentioned state value file with reference to the logical memory definition information to set state values in the above-mentioned logical memory. means for creating a simulation model from the logic memory with its state value set and circuit information necessary for effecting the state value of the logic memory in the design database; means for logically simulating the simulation model; A logic verification method comprising means for outputting the logic simulation results.