JPS6387023A - Charge comparator - Google Patents

Abstract

PURPOSE:To give no influence to the charge stored in a capacitor by producing a new channel after a transmission gate is turned off and absorbing the charge stored in the transmission gate. CONSTITUTION:A pair of complementary MOSTR (TN1 and TP1) form a switch SW1. Another pair of CMOSTR (TP11 and TN11) having a single end of its source or drain connected with the other end opened are connected to a joint (a) between the switch SW1 and capacitors C1 and C2. The signals T1d and the inverse of T1d obtained by delaying gate signals T1 and the inverse of T1 of the TRTN1 and TP1 by resistances R11 and R12 are impressed to the gates of the TRTP11 and TN11. In the same way, the TRTP21 and TN21 are connected to a joint (b) between a switch SW2 and the capacitor C1. A new channel is produced by the TRTP11 and TN11 when the gate signals of the TRTN1 and TP1 change to '0' from '1'. Thus, the charge stored in the gates of the TRTN1 and TP1 are absorbed. As a result, no influence is given to the charge of both capacitors C1 and C2.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a charge comparison circuit, and particularly relates to a charge comparison type circuit that compares charges using a capacitor, and converts an analog signal into a digital signal. It is used in A/D converters that convert signals.

(Prior art) Figure 4 shows the conventionally widely used successive approximation method (7)
An example of a comparison circuit used in an A/D converter is shown.

This comparison circuit has switches SW4 and SW5 connected in series and capacitors C1 and C2 connected in series, connected in parallel, the connection point between switch SW5 and capacitor C2 being grounded via switch SW3, and switch SW4 connected in parallel.
The analog signal VA, which is one of the comparison targets, is inputted to the connection point between the capacitor C1 and the capacitor C1 through the switch SW2, and the output VD/^ of the D/A converter, which is the other comparison target, is input to the connection point between the switch SW4 and the switch SW5. A switch SWI and an inverter INV connected in parallel are connected to the connection middle point a of capacitors C1 and C2, and the output side of INV is used as a comparison output Vou1. First, switch S
When WI is turned on, the human power of inverter INV and capacitor CI.

The connection point a with C2 becomes the circuit threshold voltage Vr of the inverter INV. During sampling, switches SW1 and SW2 . SW3 is turned on. At this time, the electric charge IArQ1 accumulated in the capacitor C1 and the electric charge Q2 accumulated in the capacitor C2 are as follows: Ql-(VA-VT)・C1...(1)C2-
−V, ·C2 (2).

Next, at the time of comparison, switches SWI, SW2 and SW3 are turned off, and switches SW4 . SW5 is turned on. At this time, the charge Q1' accumulated in the capacitor C1 and the charge Q2' accumulated in the capacitor C2 are Q1'-(VDlA-vx)・CI-...(3)
C2'-(V,,A-Vx)・C2-...(4
).

However, Vx is the potential at point a.

Here, Q1+Q2-Q1'+Q2', so ■x''
``VI) C+vT-VA' c1+c2・・・・・・(
5) If Cl-C2, then vX-■, /A+V, -wo・VA... (6). Therefore, the output voltage VD from the D/A converter
If /A is varied in the range from OV to 1/2 of the power supply voltage, the comparison output V will be obtained from the output of the inverter INV. uL can be obtained.

FIG. 5 shows the switches SW1 to SW5 shown in FIG.
S) This shows a circuit diagram when realized with a transmission gate. FIG. 6 is an electrical equivalent circuit modeled on a MOSFET, showing a gate electrode 2 formed on a gate oxide film 1 and a diffusion layer 3 forming a source and drain.
It shows various parasitic capacitances between As shown in FIG. 6, there is a parasitic capacitance QcM called Miller capacitance between the gate electrode 2 and the diffusion layer 3 forming the source and drain electrodes.
exists.

Furthermore, when the MOSFET is turned on, a channel 4 is formed, so parasitic capacitance u (c cc,
Ccl c c -c M+ CCG) is generated. Furthermore, as shown in FIG. 5, each transmission gate is a P-type MOS transistor (TPl, TP2, TP3).
) and N-type MOS transistors (TN, TN, T
N3) are interconnected and complementary gate signals T1 to T7 are applied to the respective gates. Similarly, switch SW4. SW5 is also composed of complementary MOS transistors, and each gate receives a complementary gate signal T2. T2 is applied.

Considering the parasitic capacitance shown in Fig. 6, the equivalent circuit at the time of sampling is expressed as the circuit shown in Fig. 7, and during the sampling period (T1 - "1" level) a
The charge Q at a point is Qa - (V - V) φC1
-VT@C2+ T (V -V) (CGN1+CoP1) -1
)1) T ■ ・(CcNl 10GP1)...(7).

However, when the gate signal Tt changes from the "1" level to the O" level, the charge Q at point a changes by a change in ΔQ due to the parasitic capacitance between the channel and gate of the MOSFET and the parasitic capacitance between the channel and the substrate. Here, ΔQ is ΔQ”:
(V -IV I) -CGP2+a D
D thp (V -VA) -CCP2- (V DD-
DD ■ ) @C-vAIIccN20LhN CN2 (voo-” thP ” ” CGP3-(VDD-
vthN)°CGN3+(VDD-IV 1)・C
GP1+(VD,-thp vT)"CCPI-(vDD"-vthN)"C
GNI ”-vT” CNI ・・・・・・(
8). Here, vlhN: threshold voltage of NMO8FET,
V: Threshold voltage of PMOSFET.

Although this fluctuation is a slight charge fluctuation, the inverter I
Since the fluctuation occurs near the circuit threshold of NV, it appears as a comparator error.

In order to reduce this variation, it is conceivable to design the capacitance "CP" ON between the gate, drain, and channel of the P-channel MOS and N-channel MOSFET of the transmission gate to be the same.

Assuming that the charge fluctuation ΔQa in this case is "LhN" and "LhP', CcP2-vA11CCN2 in ΔQ (vDD-VA)
+(vDD-VT)CCP1-V1·CCNI''...(9).

The first and second terms in equation (9) are due to switch SW2, and the third and fourth terms are due to switch SW1.
This is due to In this case, since the transmission gate (vDD) that constitutes the switch SWI is transmitted, the difference in charge generated in the switch SWI is due to the difference in capacitance per unit area due to the difference in substrate concentration of the P-channel and N-channel MOSFETs. ing. The error in this case is linear because the transmitted voltage is constant, and the error is linear when the A/D
It can also be reduced by taking precision measures to change the offset voltage of the converter.

However, the analog voltage VA transmitted by switch SW2
Since is any voltage from O to the power supply voltage VDD, the voltage between the channel and substrate of a P-channel MOS and the voltage between the channel and substrate of an N-channel MOS will differ depending on the voltage range. . In other words, the error disappears only when the analog voltage VA is a certain voltage, but depending on whether the analog voltage VA is higher or lower than that voltage, ΔQ appears as a - side error or a + side error, and the comparison This will lead to a loss of linearity in the precision of the circuit, causing a major problem.

(Problems to be Solved by the Invention) As explained above, conventionally, when a certain voltage is transmitted through the transmission gate, the charges generated between the channels and substrates of the P-channel MO3 and N-channel MOS transistors are different. When closed, the difference in charge causes an error in the comparator circuit.

Therefore, the present invention adopts a means to absorb the difference in charge,
An object of the present invention is to provide a charge comparison circuit that reduces errors in the comparison circuit.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a pair of complementary MOS transistors (an N-channel transistor N1 and a P-channel transistor P1).
In a charge comparison circuit configured by connecting a transmission gate consisting of a transmission gate and a capacitor whose charge/discharge is controlled by the transmission gate, one end of the source or drain is connected to the connection point between the transmission gate and the capacitor, and the other end is connected to the connection point between the transmission gate and the capacitor. The other pair of open complementary MOS transistors (N-channel transistor N2 and P-channel transistor P2) is connected, and the gate signal applied to the gate of N-channel transistor N1 is delayed and applied to the gate of P-channel transistor P2. The gate signal applied to the gate of P-channel transistor P1 is delayed and connected to the gate of N-channel transistor N2, and the gate signal applied to the gate of P-channel transistor P1 is delayed and applied to the gate of N-channel transistor N2.
2 has the same parasitic capacitance, and P-channel transistor Pl and P-channel transistor P2 have the same parasitic capacitance.

(effect)! By adopting a series of configurations, a new channel is generated after the transmission gate is turned off, and the newly generated channel absorbs the charge stored in the channel of the transmission gate, and the charge stored in the capacitor increases. It can be operated so as to eliminate the influence on the electric charge.

(Embodiment) FIG. 1 is a circuit diagram of a charge comparison circuit according to an embodiment of the present invention. Connection point between switch SWI and capacitor (a
Another pair of CMOS transistors TP each having one end of the source or drain connected to the point (point) and the other end open.
I 1. TNI 1 is connected to each gate, and a gate signal T1゜T is connected to each resistor R11' R12.
TI, delayed by .

It is configured to connect Tld. switch SW2
Regarding point b, a pair of CMOS transistors T P 21°T N 2□ are newly connected using the same connection method, and a resistor R2□ is connected to each gate.

A gate signal "ld""ld" delayed by R2□ is applied.

These new transistors replace the switch SWI, which is the cause of comparison output errors in conventional circuits.

These switches SW1. SW
2, this is added in order to set the parasitic capacitances occurring between the gate, drain, and channel to be the same as described above.

Here, in order to simplify the explanation, we will explain each part separately. Figure 2 (a) shows the new MOS l-
A circuit diagram with transistors added is shown in FIG. 2(b). An electrical equivalent circuit is shown when the gate signal T1 at TN2 changes from the "1" level to the "0" level.

In the transistors TP2 and TN2, the charge Qt2 generated between the channel and the substrate immediately before the gate signal T1 changes from the "1" level to the "02" level is QtR2-(VDDVA)・COF2- V
A-Co82.1 old...(lo), and the delay gate signal Tld becomes "0 degree level" and the delay gate signal 〒i becomes "1" level, so that the channel and substrate of transistor "21" and T N 21 The charge Qd2 generated between Q - (V - VA) ・CCTP21-d2
DD VA-CoTN2, ......(11) becomes 713 I':=t at point b is constant when the gate signal T1 becomes "0" level and the gate signal TI becomes "1" level. Therefore, the charge QtR2 is transferred to the transistor T P 21 . The charge Qd2 is generated between the channel of T N 21 and the substrate, and does not affect the charge Q1 charged in the capacitor C1.

Similarly at point a, MOSFET TPI.

TP2, TPI 1. The parasitic capacitances occurring between the gates, drains, and channels of TNI1 are set to be the same, and delayed gate signals T10. By connecting 〒4, the charge at point a remains the same as the charge at the time of sampling even if the gate signal T1 changes from the "1" level to the "0" level and the gate signal T changes from the "O" level to the "1" level. The potential at the 0 point is “0” because the N-channel MO3FET TN3 is off at the end of sampling.
level.

At this time, the P-channel MO3FET TP3 is in an off state because it is back gate biased, and no channel is formed. In addition, in transistor TN3, the channel and substrate are at the same potential, so if the gate width/gate length (W/L) of transistors TN3 and TP3 is set to be the same, the charge at point C will be Signal T1° does not vary due to changes in T1.

In this way, at the end of sampling, the charges Q1. If the fluctuation in Q2 disappears, the gate signal T2. When T2 changes to "1" and "0" levels, respectively, switches SW4. Even if the charge fluctuates due to the parasitic capacitance of the MOS transistor constituting SW5, the switch S
W4. Since SW5 is turned on, the mold ef becomes stable after a certain period of time and does not produce any errors. Therefore, a highly accurate comparison circuit can be realized.

FIGS. 3(a), (b), and (c) respectively show transistors TP11, TNII, and
TP21. FIG. 3 is a plan view showing an example of the configuration on a chip of TN21. Figures 3(a) and 3(b) each show an example when the gate width is kept at W, and the gate length is changed.The gate length is halved and the gap between the channel and the substrate is The parasitic capacitance generated between the channel and the gate electrode is halved in the case shown in FIG. 3(b).

Further, FIG. 3(c) shows the case where the gate width is reduced to W/2, and the source electrodes 10 are formed on both sides of the gate electrode 20, and these are electrically connected to equivalently show the case shown in FIG. 3(b). ) The configuration is such that a parasitic capacitance similar to that shown in FIG.

In the above embodiments, the comparison circuit used in a successive approximation type A/D converter was explained as an example.
The present invention can be easily applied to other types of A/D converters as long as they use a comparison circuit including a capacitor and a transmission gate.

〔Effect of the invention〕

As described above in detail based on the embodiments, in the present invention, a new CMOSFET is connected as a pair to the MOSFET constituting the transmission gate, and the phase of the gate signal applied to the transmission gate is inverted to the gate electrode of the new CMOSFET. After the transmission gate is turned off, a new channel is generated in the added 0MO3FET to absorb the charge stored in the channel of the transmission gate. The charge stored in the capacitor does not change due to changes in the input signal. Therefore, it is possible to construct a charge comparison circuit having a stable and highly accurate comparison output.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a comparison circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of the comparison circuit shown in FIG. 1 and its equivalent circuit diagram, and FIG. M added to
A plan view showing the pattern layout of the OSFET, FIG. 4 is a schematic configuration circuit diagram of a conventional comparison circuit, FIG. 5 is a detailed circuit diagram of the circuit shown in FIG. 4, and FIG. 6 is a configuration diagram modeling a MOSFET. FIG. 7 shows equivalent circuit diagrams of the conventional comparator circuit at the time of sampling. CI,, C2... Capacitor, TPI, TNI...
CMOS transistor TP that constitutes switch SWI
2. TN2...CMOS transistor constituting switch SW2, TPII, TNII...switch SW1
A newly added CMOS transistor, TP21.
TN21...CM newly added to switch SW2
OS transistor, applicant's agent Mr. Sato (b) 3 Figure Analog signal A D/A Co. 1st 4 Figure column 5

Claims (1)

[Claims] 1. A charge constructed by connecting a transmission gate consisting of a pair of complementary MOS transistors (N-channel transistor N_1 and P-channel transistor P_1) and a capacitor whose charging and discharging is controlled by the transmission gate. In the comparison circuit, another pair of complementary MOS transistors (an N-channel transistor N_2 and a P-channel transistor P_2) each have one end of their source or drain connected to the connection point between the transmission gate and the capacitor and the other end open.
), a gate signal applied to the gate of the N-channel transistor N_1 is delayed and applied to the gate of the P-channel transistor P_2, and a gate signal applied to the gate of the P-channel transistor P_1 is delayed. The N-channel transistor N_1 and the N-channel transistor N_2 have the same parasitic capacitance, and the P-channel transistor P_1 and the P-channel transistor P_2 have the same parasitic capacitance. A charge comparison circuit characterized in that it is configured so that parasitic capacitances are the same. 2. The charge comparison circuit according to claim 1, wherein the gate signal is delayed by a resistor.