JPS6386478A - Manufacture of insulating gate type semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration by forming a gate electrode on the side wall part of a recess formed in a predetermined region on a semiconductor substrate of a first conductivity type, and, with this electrode as a mask, ion-implanting an impurity of a second conductivity type into the substrate surface thereby to form source and drain regions. CONSTITUTION:After forming an oxide film 2 on the surface of a substrate 1, a resist film 20 having a hole section is formed, and with the film 20 as a mask the substrate 1 is anisotropically etched to form a recess. Then, after removing the film 20, an insulating film 4 is formed on the substrate 1 surface, and further a silicon layer 5 is formed. And, a resist film 21 is formed in the portion in which a gate electrode is to be drawn out. Then, by performing anisotropic etching, leaving the silicon layer 5 on the side wall part of a recess 3 and the part having the photoresist, the other part is removed, thereby forming an electrode 50. And the electrode 50 as a mask As ions 6 are implanted to form source and drain regions 7, 7. Subsequently, after forming an insulating film 8 on the surface, an opening 9 is provided, and a wiring layer 10 is formed. With this, the gate width can be changed without varying the area occupied by the device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an insulated gate type semiconductor device such as an MO8 field effect semiconductor device.

[Prior Art] FIGS. 68 to 6C are process cross-sectional views showing a conventional method of manufacturing a ~10S semiconductor device. 7 and 8 are plan views of the steps shown in FIGS. 6B and 6C. Below, with reference to these figures, the conventional MO8
A method for manufacturing a semiconductor device will be explained.

First, as shown in FIG. 6A, the LO is placed on the p-type silicon substrate 1.
An oxide film 2 for element isolation is formed using the CO8 method. Next, as shown in FIG. 6B, a goo 1-insulating film 4 is formed on the p-type silicon substrate 1, an n-type polysilicon is formed thereon, and this is etched using a photoresist. A gate electrode 51 as shown in FIG. 7 is formed. Resist 1vI! After leaving the As ion at 150keV
r4x10” cl-2 injection to source train region 7
Form ゜7. Then, as shown in FIG. 6c, an insulating film 8 is further formed on the upper surface, and a contact hole 9 is opened at a predetermined location in the insulating film 8, thereby forming an aluminum wiring w11o as shown in FIG. . In the manner described above, the device is completed.

[Problems to be Solved by the Invention] In the conventional MO8 semiconductor device manufactured in this way, the gate is formed on a plane, so by changing the gate length and gate width, the area occupied by the element can be reduced. Therefore, it was not possible to easily change the gate length or gate width. Furthermore, since increasing the gate length and gate width increases the area occupied by the element, there is a problem in that the degree of integration cannot be expected to improve.

This invention was made in order to solve the above-mentioned problems, and it is possible to manufacture an insulated gate type semiconductor device in which the area occupied by the element does not change even if the gate length or gate width is changed, and the degree of integration can be improved. The purpose is to provide a method.

[Means for Solving the Problems] In the method for manufacturing an insulating goo type 1-type semiconductor device according to the present invention, a recess is formed in a predetermined region on a semiconductor substrate of a first conductivity type, and a gate is formed on the side wall of the recess. Source and drain regions are formed by forming an electrode and ion-implanting impurities of a second conductivity type into the surface of the semiconductor substrate using the gate electrode as a mask.

[Function] According to the method for manufacturing an insulated gate type semiconductor device according to the present invention, a gate is formed on the side wall of the recess, the gate length corresponds to the depth of the recess, and the gate width corresponds to the length of the periphery of the recess. It turns out. Therefore, by changing the depth of the recess, the gate length can be changed, and by changing the planar shape of the recess, the gate width can be changed.

That is, if the concave portion is formed in a planar shape such that the circumference becomes long, the gate width can be increased.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

Figures 18 to 1E show an embodiment of the present invention.
FIG. 3 is a cross-sectional view of main steps in a method for manufacturing an O3 semiconductor device. Also, Figure 2 (a), (tl), Figure 3, Figure 4, and Figure 5.
The figure is a plan view of each step in FIGS. 1B to 1E. Hereinafter, a method for manufacturing the MO8 semiconductor device will be described with reference to these figures.

First, as shown in FIG. 1A, oxide [12] for element isolation is formed at predetermined locations on the surface of the p-type silicon substrate 1. Next, as shown in FIG. 1B, a photoresist 1I20 having holes of a predetermined shape is formed, and this photoresist group 20
The concave portion 3 is formed by anisotropically etching the p-type silicon substrate 1 using as a mask. FIG. 2(a) shows a case where the recess 3 is formed into a square shape.

The depth of this recess 3 corresponds to the gate length.

Next, as shown in the first CliJ, after removing the photoresist group 20, a gate insulation m4 is formed on the surface of the p-type silicon substrate 1, and further an n-type polysilicon ld5 is formed. Then, a photoresist film 21 is formed on the portion where the gate electrode is drawn out (see FIG. 3). Next, as shown in FIG. 1D, anisotropic etching is performed using RIE (reactive ion etching) to remove the sidewalls of the recesses 3 and the photoresist layer 5, leaving the remaining portions. In this way, gate electrode 50 is formed. And this gate electrode 5
0 as a mask, for example, As ions 6 are implanted at 150 eV to form source and drain regions 7.7 (
(See Figure 4). Then, as shown in Figure 1E, the surface is insulated [! After forming source and drain regions 7
．． 7 and an opening 9 (contact hole) for making electrical connection with the gate electrode 50, and an aluminum wiring FIJ10 is formed (see FIG. 5). The device is completed in the above manner.

The gate length of the device formed in this way is determined by the depth of the recess 3, and therefore, even if the gate length is changed, the area occupied by the device does not change.

Further, the gate width of this element is determined by the length of the circumference of the recess 3, and therefore, the shape of the recess 3 can be changed in order to change the gate width. Figure 2(b)
If the recess 3 is formed in the shape of □, the area of the side wall of the recess 3 can be increased, and therefore the gate width can be increased.

Although the above embodiment describes an N-channel insulated gate (MOS) semiconductor device, by changing the p-type silicon substrate to an n-type silicon substrate and changing the implanted impurity from n-type to p-type, P-channel MO3 It is also applicable to semiconductor IAI.

[Effects of the Invention] As described above, according to the present invention, the gate is formed on the side wall of the recess, and the gate length is determined by the depth of the recess. The area remains unchanged. Furthermore, since the width is determined by the length of the periphery of the recess, by changing the planar shape of the recess, the gate width can be changed without changing the area occupied by the element.

Therefore, even if the gate length and gate width are increased, the area occupied by the element does not increase, and an improvement in the convergence of V4 degrees can be expected.

[Brief explanation of the drawing]

FIGS. 18 to 1E are process cross-sectional views showing one embodiment of the method for manufacturing a gate insulated semiconductor device according to the present invention. Figures 2(a)(b), 3, 4 and 5
The figures are plan views corresponding to FIG. 1B, FIG. 1C, FIG. 1D, and FIG. 1E, respectively. Figures 68 to 6C
I is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device. Figures 7 and 8 are Figures 68 and 6, respectively.
It is a top view corresponding to figure C. In the figure, 1 is a first conductive type semiconductor substrate, 3 is a recessed portion, and 4 is a semiconductor substrate of a first conductivity type.
6 is the gate isolation fill, 6 is the second conductivity type impurity ion,
50 is a gate insulating film. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masu Oiwa Condolences IA Figure LB Figure 20 Figure 4 Tsuji 5 Figure 6A Figure 6B

Claims (4)

[Claims] (1) Forming a recess in a predetermined region on a semiconductor substrate of a first conductivity type, forming a gate insulating film on the semiconductor substrate, and forming a gate electrode on the side wall of the recess on the gate insulating film. A method for manufacturing an insulated gate type semiconductor device, comprising the steps of: ion-implanting an impurity of a second conductivity type into the surface of the semiconductor substrate using the gate electrode as a mask. (2) The gate electrode is formed by forming an electrode material layer on the semiconductor substrate and the gate insulating film, forming a photoresist on the electrode extraction area, and then performing anisotropic etching to leave the recessed sidewalls and the electrode extraction area. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by removing other electrode materials. (3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the electrode material is a semiconductor or a high melting point metal. (4) The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the recess is formed in a shape that increases the area of the side wall.