JPS6386043A - Memory device with sorting mechanism - Google Patents

Abstract

PURPOSE:To realize effective application of resources by forming memory devices of a hardware sorter into a multi-port and making various devices in an electronic computer system share those memory devices. CONSTITUTION:The ports 24-26 excepting for sorting processors of memory devices 14-16 out of those memory devices 11-16 of a hardware sorter 20 are connected to a memory bus 40 and used as disk caches. Under such conditions, the data on a disk device 30 are read out by a disk controller 31 and written to the devices 14-16 through ports 24-26. When a flow of data received from the device 30 is sorted by the sorter 20, the data are read out of the device 30 by the controller 31 and inputted to the sorter 20. The results of pipeline merge sorting jobs carried out successively via sorting processors P11-Pn6 and devices 11-16 are outputted to a bus 40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device that can be used in multiple ways for a hardware sorter that executes sorting processing performed on a computer at high speed.

[Conventional technology]

Figure 3 shows the Journal of the Institute of Electronics and Communication Engineers, J66-D (1983
This is an example of a configuration diagram of the conventional hardware sorter shown in Fig. 1, in which (1) to (5) ha sort processors, IIυ to a are memory devices used by each sort processor. be.

Next, the operation will be explained. Now, suppose that N (-2”) records are to be sorted. 2-way merge
Prepare n (-Z o g 2 N processors) and combine them in a one-dimensional manner. The first processor has a memory for two records. That is, M11Iυ is for two records, M2CI3H2L/: !-)'min, M5α9
has memory for 2-16 records. The N records are serially input to the first processor P1ill, and the first processor merges the two sorted strings of 2 unique records sent from the 1-1st processor. A string consisting of 2 records is generated and sent to the 1st+1st processor.

In this way, the hardware sorter in FIG. 3 sequentially executes pipeline merge sort.

[Problem that the invention seeks to solve]

The memory device of a conventional hardware sorter is configured as described above, and each processor in each stage has its own dedicated memory device Ek, and the processor cannot be used for any purpose other than performing sort processing. For example, when using a hardware sorter with more than 10 stages of processors and only a few MB of memory in a computer system that includes a disk device, the memory cannot be used by other devices, and shared resources cannot be used effectively. There was a problem.

The present invention has been made to solve the above-mentioned problems, and includes a device 1 that uses a hardware sorter, such as a disk control device or a central processing unit.

Alternatively, it is an object of the present invention to obtain a memory device having a sorting mechanism that can be used in multiple ways by each raccoon microprocessor or the like as its own H memory space.

[Means for solving problems]

By providing a multi-port access path, the memory device having a sorting mechanism according to the present invention can be used not only as a memory for a hardware sorter but also as a memory space for other devices. be.

[Effect]

In the present invention, by making a memory device having a sorting mechanism multi-ported, various devices within a computer system can use the memory device, and resources can be shared and used effectively.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an example in which a hardware sorter is connected to a disk device.

(to) is a hardware sorter, (1) to (6) are each sort processor consisting of n stages, I to αQ are memory devices,
04) to (a) are ports other than the sort processor of the memory device. As a peripheral device of the hardware sorter, disk device 01. Disk control device Cl11.
゛System control device (41) that performs data input/output control, etc.

There is a channel interface (42) for connecting to other host computers. The data transfer path between these devices is the memory bus C1, the transfer path C (3) between the disk device ■ and the disk control device C1υ, the output path (from the disk control device to the hardware sorter), and the disk control device 00 and the memory. Bus (transfer route (b) with 4 (I).

There is a sort result output path (to) from the hardware sorter (1), a channel interface (42), and a transfer path (43) to the host computer.

Next, the operation will be explained.

First, a case will be described in which a data stream from a disk device is sorted using a hardware sorter. The data in the disk device (to) is transferred to the disk controller G.
It is read out from data transfer path 0 by υ and input to the hardware sorter, cXJ, through the data transfer path (to). In the hardware sorter (1).

Pipeline margin is performed in order using each sort processor P, (1) to Pn (6) and the memory device υ (Iet-) of each processor, and the sort results are transferred to the memory bus (41) through the data transfer path The data is read and processed by the system control device (41), or sent to the host computer via the channel interface (42) fc and the data transfer path (43) fjc.

FIG. 2(a) shows such a sorting mode.

Next, the case of using it as a disk cache will be explained. The data in the disk device (to) is read from the data transfer path 03 by the disk controller OD, output to the memory bus via the data transfer path (b), and then transferred to the memory device in the hardware sorter (4). α fathom~8
0, baud)04)~@all written. In this way, a copy of the data in the disk device (to) is placed in the memory devices I to αQ.

On the other hand, data in the disk drive is read from the host computer via the channel interface (42), and if the data is a hit.

Data is immediately sent to the host computer via the memory device (14-H to baud) C19-@ to the memory bus Gt (I) via the channel interface (42) and data transfer path (45).

The data in the disk device (7) is read by the disk controller No. In this way, normal disk cache memory control is performed. These controls are managed by a system controller (41).

Such a disk cache mode is shown in FIG. 2(b).

In the above embodiment, the case where the memory device is used as an all-disk cache was explained.

Transfer the memory device boat to another device that requires memory 1
For example, it may be used as a memory access port of a central processing unit of a host computer, allowing multiple use of the memory space of the memory device.

〔Effect of the invention〕

As described above, according to the present invention, since the memory device of the hardware sorter has a multi-port configuration, it is not necessary to add a large hardware device in a hardware sorter environment where data in a disk device is sorted. It can provide high-speed, large-capacity memory space such as disk cache without requiring it.

This has the effect of making it possible to use resources more effectively and realizing higher performance, simplification, and lower cost of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing an example of how the memory device is used by mode. FIG. 2(a) is a diagram showing the sort mode, FIG. 2(b) is a diagram showing the disk cache mode, and FIG. 3 is a diagram showing the configuration of a conventional hardware sorter. In the figure, (1) to (6) are sort processors, 1ll
) ~ (IG is a memory device, 翰 is a hardware sorter,
Q4~@ are access ports of the memory device. ■ is a disk device, 01) is a disk control device, 0 is a data transfer path, G11) is a memory bus, (41) is a system control device, and (42) is a channel interface. (43) is a data transfer path with the host computer. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] By making the memory device of a hardware sorter that performs high-speed sort processing on a computer system multi-ported, the memory device can be shared by various devices that require memory functions within the computer system. A memory device having a sorting mechanism characterized by comprising: