JPH01303521A - Hardware sorter unit - Google Patents

Abstract

PURPOSE:To facilitate the packaging of a hardware sorter unit onto a substrate by arraying an input pin train on one of a pair of relative sides of a tetragonal sort processor transformed into an LSI together with an output pin train set on the other side. CONSTITUTION:An output pin train 11b of a sort processor 1 set at the preceding stage is connected to an input pin train 11a together with the input pin train 11a of the processor 1 set at the next stage connected to the output pin train 11b respectively. Thus these pin trains are arrayed along a data flow 12. At the same time, a local memory 13 is set at the left of the flow 12. In such a constitution, the local memories M1-M12 of the sort processors P1-P12 ranging from the 1st stage through the 12th stage have small capacities. Then the capacity equal to the design record length of the memory M12 of the final stage is used. As a result, the packaging a hardware sorter unit is facilitated onto a substrate with use of the memories of the same size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a hardware sorter unit for sorting a large amount of data with a hardware configuration using a dedicated sort processor and a plurality of local memories;
In particular, it relates to the board implementation of the sort processor and local memory.

[Prior art] Figure 4 shows, for example, the technical research report of the Institute of Electronics and Communication Engineers dated September 26, 1986 (IEICE Technical Report Vol. 1.86. No. 170).
), a schematic configuration diagram showing a conventional hardware sorter described in CPSY-26, and FIG. 5 is an implementation configuration diagram thereof.

In the figure, (1) is TTL-5SI/MSI with substrate 1
Sort processor P1 (i=1-n) mounted on
The total number of sort processors PL is 18 stages (n=18).
It consists of (2) is a data flow that connects these sort processors in a pipeline form (a state in which data flows continuously in synchronization with the control clock), and (3) is a local memory Ml for each sort processor P (i=
1 to n), sort processor P from stage 1 to stage 12
1 ~ Pi2 local memory M engineering ~ M z z is RAM
is mounted on the same board as the sort processor, and the local memories from the 13th stage onwards are mounted on a separate board from the sort processor. And the storage capacity of each local memory′! For example, in iMl, the design length of the sort record is 32.
Assuming B (byte), M1 = 328° M2 = 32BX
2=648. M,=32BX2"=128B,...9
M1□= 32B x 2” press 2MB, M,, =
32B
This has increased by a factor of 1. In the figure, diagonal lines on the memory board indicate the memory section. (4) is a sorter unit consisting of these sort processors and local memory, and together with a sorter drive device (5) constitutes a sorter system consisting of 29 boards. (6) is a control line from the sorter drive (5) to each sort processor (1);
) is an external memory bus for accessing the local memory (3) from external memory.

Next, the operation will be explained. Assume that N (=2r') records are to be sorted. In the case of Figure 5, n=
18, it is possible to sort 250,000 records with N = 262,144 valves. The data consisting of these N records continuously flows through data flow (2) and is serially input to the sort processor P□ starting from the first record. In the first sort processor P, the first record is loaded into the local memory M1, this loaded record and the second input record are sorted, and the sorted 2-record length 1-string data is processed. is output to the next sort processor P2. In this way, sort processor P1 selects the third and fourth records, the fifth and sixth records, and so on.
Sorting is performed record by record, and the sorted data of one string with a length of two records is sequentially output to the next sort processor P2.

In the sort processor P2, the first and second input
The string obtained by sorting the th record is loaded into the local memory M□, and the second string obtained by sorting this loaded string and the 3rd and 4th records to be input next is sorted, and the sorted string is sorted. Data of 4 records long and 1 string is output to the next sort processor P3□. In this way, sort processor P2 sorts two strings with a record length of 2, sort processor P sorts two strings with a length of 4 records, and sort processor Pi sorts two strings with a record length of (i-1). It is performed along with the flow of data flow (2), and is the Nth.

That is, the 188th sort processor P1. So 13107
Two strings with a length of two records are sorted, and sorted data with a length of 262,144 (=N) records is obtained as the final output.

In this way, approximately 260,000 records are sorted at once along with the data flow (2), and the time required for this is approximately 2 seconds since the throughput is 4 MB/see.

[Problems to be Solved by the Invention] The conventional hardware sorter unit is configured as described above, and the capacity of the local memory mounted in each stage increases by a factor of 2, making it difficult to implement. As the number increases, the equipment becomes enormous. Therefore, the sort processor is LSI
However, if it is implemented on an LSI, it is necessary to maintain the continuity of the sort processor's pipeline, implement local memory at high density, and make it easy to deploy control microcode. However, there is a problem in that it is difficult to create an arrangement that satisfies such requirements.

This invention was made to solve the above-mentioned problems, and it is possible to maintain pipeline continuity of data flow, flexibly respond to changes in the local memory capacity of each stage sort processor, and The object of the present invention is to obtain a hardware sorter unit that can be easily mounted on a computer.

[Means for Solving the Problems] In the hardware sorter unit according to the present invention, each sort processor is formed of a quadrilateral LSI, and an input pin array is connected to one of a pair of relative sides of the quadrilateral, and an output pin is connected to the other side. A row of pins is arranged, and a row of connection pins for local memory is arranged on one side perpendicular to this relative side, and a row of pins for control microcode input/output is arranged on the other side. The first sort processor is arranged on the input pin side, the second sort processor is arranged on the output pin side, and each local memory is arranged on the connection pin side with the local memory, respectively, on the same board.

Further, in the above configuration, it is preferable that the sort processor is arranged at the periphery of the board, and these local memories are arranged at the center of the board.

Furthermore, in the above configuration, where the number of sort processors has a small number of stages below a predetermined number, the arrangement can be further facilitated by using local memories with the same capacity that is greater than or equal to the required storage capacity of each.

[Work] The hardware sorter unit in this invention is:

Since the input pin array is arranged on one side of the pair of relative sides of the LSI-shaped quadrilateral sort processor, and the output pin is arranged on the other side, each sort processor can be arranged along the data flow and continuity of the pipeline can be maintained. At the same time, the local memory connection pin row is arranged on one side of the other pair of relative sides, and the control microcode input/output pin row is arranged on the other side, so that the local memory of each stage can be placed on the same side of the data flow. This makes it possible to arrange them on the top, making it easier to connect them to control lines.

Furthermore, by arranging sort processors at the periphery of the board and arranging local memories at the center of the board, it becomes possible to mount them in response to changes in their capacity.

Furthermore, by making the local memories of sort processors with a small number of stages near the first stage have the same capacity, the sorter units consisting of sort processors with a predetermined number of stages or less can be arranged with local memories of the same size as JR41! The sorter unit, which includes sorting processors after a predetermined number of stages, is mounted on a board that corresponds to a change in the capacity of the local memory.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
FIG. 2 is a plan view showing a schematic configuration of a sort processor used in an embodiment of the present invention, FIG. 2 is a schematic configuration diagram showing the arrangement of parts near the first stage of an embodiment of the invention, and FIG. FIG. 2 is a schematic configuration diagram showing the arrangement of components after a predetermined number of stages in one embodiment. In the figure, (10) is the quadrilateral L
The sort processor (11) is the input/output pin array of the sort processor composed of SI (large scale integrated circuit), and the input to one (10a) of the pair of relative sides (10a) (10b) of the sort processor (10). The pin row (lla) is connected to the other (10b)
) is the output pin row (llb), and the remaining relative side (10c)
A local memory connection pin row (lie) is arranged on one side (10c) of (10d), and a control microcode input/output pin row (lid) is arranged on the other (10d). (12
) is a pipeline data flow, (13) is a local memory, (14) is a board, (15) is a control line for control microcode input/output from a sorter drive device (not shown), (16a) ) are the sort processors P1 to P□2 from the first stage to the 12th stage and their local memories M1 to M□2 on the same board (14).
The first sorter unit (16b) mounted in the 13th to 18th stage sort processors P13 to P18 and their local memories M13 to M1. on the same board (
This is the second sorter unit installed in 14).

As shown in FIGS. 2 and 3, the sort processor (1) shown in FIG.
llb) is the input pin array of the subsequent sort processor (llb).
a) is connected, it will be arranged along the data flow (12), and the local memory connection pin row (ll
Since the local memory (13) is arranged on the c) side, the local memory (13) is arranged on the left side in the direction of the data flow (12). Therefore, since the capacity of the local memories M1 to M1□ of the sort processors P1 to P12- from the 1st stage to the 12th stage is small, the capacity is the same as the designed record length of the last stage local memory M12. This facilitates implementation by using standardized memories of the same size and arranging them as shown in FIG. From the 13th stage onwards, as shown in Figure 3, the board (14
) local memory M, 3~MyuI (1
3), and a sort processor P1. ~P
By arranging (10) along the data flow (12) so as to surround the local memory (13), the continuity of the pipeline of the data flow (12) is maintained while High-density packaging becomes possible. In addition, by arranging the control line (15) on the opposite side of the local memory (13), it becomes easy to connect it to the control microcode input/output pin array (LID) of each sort processor (lO). . Furthermore, the data flow (12) of the first sorter unit (16a) shown in FIG. 2 and the second sorter unit (16b) shown in FIG.
By reversing the direction of both units (16a
), (16b) can be connected to each other through the backboard or front cable, allowing for flexibility in system configuration by allowing variations such as sorting by only one board or sorting by two or more boards. is giving.

It should be noted that the basic operation of the sorting process in this embodiment is the same as that in the conventional example, so a specific explanation will be omitted.

The number of stages of sort processors in the first and second sorter units shown in the description of the above embodiments is 12 and 6.
It goes without saying that this is merely an example and is not limited to this.

Furthermore, in the above embodiment, local memories of the same capacity are used up to a predetermined number of stages, but it is also possible to use memory elements whose capacity increases from the first stage, as shown in FIG. .

Furthermore, by mounting the first and second sorter units shown in FIGS. 2 and 3 on both sides of a single board, higher density mounting becomes possible.

[Effects of the Invention] As described above, according to the present invention, the input pin array is arranged on one side of the pair of relative sides of the quadrilateral sort processor converted into LSr, and the output pins are arranged on the other side, so that each sort processor can be It can be arranged along the data flow to maintain the continuity of the pipeline, and the connection pins for local memory are arranged on one side of the other pair of relative sides, and the control microcode input/output pins are arranged on the other side. Therefore, it becomes possible to arrange the local memories of each stage on the same side of the data flow on a plane, and there is an effect that the connection with the control line becomes easy.

In addition, by arranging local memory in the center of the board and arranging sort processors around it at the periphery of the board, it becomes possible to implement high-density packaging that accommodates these changes in capacity. By making the local memories of sort processors with a small number of stages the same capacity, sorter units consisting of sort processors with a predetermined number of stages or less can be mounted on a standardized board on which local memories of the same size are arranged, and can be constructed at low cost. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a schematic configuration of a sort processor used in an embodiment of the present invention, FIG. 2 is a schematic configuration diagram showing the arrangement of parts near the first stage of an embodiment of the present invention, and FIG. FIG. 4 is a schematic configuration diagram showing the arrangement of components after a predetermined number of stages in an embodiment of the present invention, FIG. 4 is a schematic configuration diagram showing a conventional hardware sorter, and FIG. 5 is an implementation configuration diagram thereof. In the figure, (10) is a sort processor, (10a
)(10b) is its pair of relative sides, (10c)(10
d) is the remaining relative edge, (lla) is the input pin array, (ll
b) is the output pin row, (llc) is the local memory connection pin row, (lid) is the control microcode input/output pin row, (12) is the data flow, (13) is the local memory, (14) is the board, (15) is the control line, (
16a) is the first sorter unit, (16b) is the second sorter unit
This is a sorter unit. The same reference numerals in the figures indicate the same or corresponding parts.

Claims (3)

[Claims] (1) n sort processors P_i (i=1 to n) are serially pipeline-coupled, and each sort processor has a local memory M_i (i= 1-n), each of the sort processors is made of a quadrilateral LSI, with an input pin array on one of a pair of relative sides of the quadrilateral, and an output pin array on the other side. A row of connection pins for connecting to the local memory is arranged on one of the relative sides perpendicular to this relative side, and a row of pins for control microcode input/output is arranged on the other side, and the input pins of each of these sort processors are arranged. The front-stage sort processor is on the side, and the rear-stage sort processor is on the output pin side.
Connect each local memory to the connection pin side with the local memory,
A hardware sorter unit characterized in that each is arranged on the same board. (2) The hardware sorter unit according to claim 1, wherein the sorting processor is arranged at the periphery of the board, and the local memories are arranged at the center of the board. (3) A hardware sorter unit according to claim 1 or 2, wherein the local memories of the sorting processors at a predetermined stage and earlier have the same capacity, which is greater than or equal to the required storage capacity of each of the sorting processors.