JPS6382172A - Semiconductor scanning circuit - Google Patents

Abstract

PURPOSE:To vary number of delay stages of a semiconductor scanning circuit by an external control signal by adding 3rd and 4th FETs for control to a flip-flop circuit. CONSTITUTION:One stage of the flip-flop consists of the 1st-4th FETs 1-4 and 1st and 2nd inverters 5, 6. In operating the 4-stage as a 2stage semiconductor scanning circuit, it is attained by having only to set control inputs 21 and 23. With the control inputs 21, 23 to be set, the 3rd and 4th FETs of the flip-flop circuit are turned on, the flip-flop circuit of the stage acts like a single buffer, the output lines 14,15 have the same delay output and output lines 16,17 have the identical delay output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a scanning circuit consisting of a large number of 7 logic flop circuits is integrated on a semiconductor substrate.

[Summary of the invention]

The present invention is an electric device in which the number of delay stages of the semiconductor scanning circuit can be varied by an external control signal by adding a 37th ΣT and a 41st FET for control to the flip-flop of the semiconductor scanning circuit.

[Conventional technology]

FIG. 3 shows a circuit diagram of a conventional semiconductor scanning circuit. In a conventional semiconductor scanning circuit, one stage of 7 ring flops is the first FBT1.
And the second FF! The scanning circuit was composed of T2, a first inverter 5, and a second inverter 6, and 7 rigs and 70 tubes were connected in series according to the required number of stages of the scanning circuit to form a scanning circuit.

To explain the operation of the scanning circuit, the signal inputted by the data input 13 is inputted by the first FET, t, and the first clock 1, and as the first clock changes from the on state to the off state, it becomes the input of the first inverter. Retained. Next, the signal transmitted by the first inverter is held at the input of the second inverter by opening and closing the 27th FiT and the second clock. The signal transmitted to the output of the second inverter is input to the next stage flip-flop. Through the above operation, the signal input to the data input 15 is transmitted to each flip-flop, and by passing through the required number of stages, an output signal delayed by the desired number of stages is obtained.

[Problem that the invention seeks to solve]

In a conventional semiconductor scanning circuit, for example, if the semiconductor scanning circuit is configured with 100 stages of 7 lip-flops,
If you want to get the output from the 50th stage in the middle, you will need wiring to take out the output from the 50th stage. Furthermore, if the outputs of a scanning circuit with a certain number of stages are connected, in order to change the delay time of the scanning circuit at each output, the wiring must be changed or the number of delay stages of the scanning circuit must be changed. did not become. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems and provide a semiconductor scanning circuit in which the delay time can be changed by an external control signal without changing the wiring or the number of delay stages of the semiconductor scanning circuit. That's a thing.

[Means for solving problems]

A semiconductor scanning circuit according to the present invention includes α) a semiconductor scanning circuit having a plurality of flip-flop circuits arranged in a two-dimensional manner, b) the flip-flops are a first FET, a second FET, a third FET, and a fourth FET;
C) First FF! T and the 4th FF1T source is the 1st
connected to the input of the inverter, and the output of the first inverter is connected to the drains of the 211th FET and the 31st FET;
The sources of the second and third IFETs are connected to the input of the second inverter, the gate of the first ynT is connected to the first clock, the gate of the 21st FET is connected to the second clock, and the sources of the third and fourth IFETs are connected to the second clock. The gate is characterized in that it is configured to be connected to a control input.

[Effect]

To describe the operation of the present invention, as shown in Fig. 1, one stage of 7 rigs and 70 tubes has
It is composed of one FET and first and second inverters.

FIG. 1 shows only four stages of the clip 70. For example, when these four stages are operated as a two-stage semiconductor scanning circuit, the control manual 21 and the control manual 2
Just turn on 3. When control human power 21 and 23 are turned on, the 37th F of the 7 rig 70 tube circuit! T
, the lI4FET turns on, and the 7 rig 7 of this stage
The 0 tube circuit acts simply as a buffer, and the output line 14
and 15 have the same delayed output, and output lines 16 and 17 also have the same delayed output. This state is shown in the timing chart of the semiconductor scanning circuit in FIG.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

The semiconductor scanning circuit of the present invention is composed of a plurality of 7 lip-flop circuits arranged one-dimensionally.
! It is composed of the BT-3, the 471st!1T-4, the first inverter 5, and the second inverter 6. 11th FE
The gate of T is connected to the first clock 12, and the gate of the 21st FE
The gate of T is connected to the second clock 12, and the gate of T is connected to the second clock 12. i? E
T and Jl? ET gate is control input 21-2
4 and 7 lip-flops are connected to each stage. The sources of the first FET and the 41st FMiT are the first inverter 5.
0 input, the drains of the second FET and the third FET are connected to the output of the first inverter 5, the sources of the second FET and the third IFFiT are connected to the second inverter 60 input, and the output of the second inverter 6 is connected to the This is the input for the stage.

When all control inputs 21 (721) to 24 (V24) are off, the signal V13 input to the data input 13
is the first clock 11 (Vll) and the second clock 12 (7
12), resulting in a signal that is delayed one step at a time as shown in the timing chart of FIG.
~17 have different timing signals V14.
, Vl 5 , Vl,6 and Vl7 are output. When control inputs 21 (V21) and 23 (723) are on and 22 (V22) and 24 (V24) are off, the first and third stage flip-flop circuits act as mere buffers, and the output line A signal ■14°Vl5 having the same timing as the output line 14 is output to the output line 15, and the output line 17
There are signals Vi 6 and V at the same timing as the output line 16.
l7 is output, and the total number of delay stages is half that of the case where all control inputs 21 to 24 are off.

In one embodiment of the invention shown in FIG. 1, the control inputs are 21
Although it is composed of 4 pieces, 24 to 24, it may be composed of as many pieces as necessary. Also the 1st FF! Although the T-41st FET is configured with N channels for convenience of explanation, it may also be configured with P channels, or a circuit with the same operation can be configured with a combination of P channels and N channels.

FIG. 2 shows an embodiment in which the semiconductor scanning circuit of the present invention is applied to a solid-state imaging device. 200 and 300 in FIG. 2 are constituted by semiconductor scanning circuits of the present invention, and horizontal switches 31 are signal line selection switches arranged one-dimensionally;
32 and 33 are vertical switches and photodiodes, respectively, and 32.degree. 53 is a plurality of vertical switches arranged two-dimensionally.

In solid-state imaging devices using conventional semiconductor scanning circuits, it was necessary to change the wiring to change the number of bits in the horizontal and vertical directions, but with the semiconductor scanning circuit of the present invention, external With the electrical signal from 21-2
4 and the horizontal side by controlling the control inputs 211 to 214.

The number of bits on the vertical side can be changed freely.

Therefore, it becomes possible to extract a plurality of optical characteristics from one solid-state imaging device, greatly expanding the range of applications.

〔Effect of the invention〕

Since the semiconductor scanning circuit of the present invention can change the number of delay stages of the scanning circuit by external electrical control, there is no need for design changes such as changing wiring or changing the number of delay stages, increasing design margin. It has a great effect on expansion and cost reduction.

Furthermore, when applied to a solid-state imaging device, the optical characteristics can be changed freely, which has the effect of greatly expanding the range of applications.

[Brief explanation of the drawing]

112. Circuit diagram of a semiconductor scanning circuit showing an embodiment of the present invention. FIG. 2. Circuit diagram showing an embodiment of the present invention. FIG. 3: Circuit diagram of a conventional semiconductor scanning circuit. Circuit timing chart...i-th FF1T 2...2nd FET 3...3rd FET 4...4th FET 5...1st inverter 6...Second inverter 11...First clock 12...Second clock 13...Data input 14...First output line 15...Second output line 16... ...Third output line 17...Fourth output line 21...First... Control human power 22...Second control human power 23...Sixth control human power 24...Fourth control input 200...Horizontal side semiconductor scanning circuit 300...Vertical side conductor scanning circuit 111... ...First clock 121...Second clock 131...Data input 211...First control input 212...
-Second control human power 213...Third control human power 214...Fourth control human power 141...First output line 151...Second output line 161...Third output line 171...Fourth output line 61...Horizontal switch 32...Vertical switch 63...・・・・・・Photodiode 34.44,
54゜64... Vertical signal line 60...
...Output signal line 100...7 Rig flop circuit 1 stage V11.
...First clock signal 712...Second clock signal '713...Data input signal Vl 4.715, Vl 6, Vl 7...
- Output signals of output lines V21, V22, V23, V24... Control input signal '75. V51, VS2. VS2...First inverter output signal or higher Applicant: Seiko Epson Corporation figure

Claims (1)

[Claims] (a) In a semiconductor scanning circuit having a plurality of flip-flop circuits arranged in a one-dimensional manner, (b) in which the flip-flop circuit is a first field-effect transistor (hereinafter referred to as a field-effect transistor). )
(c) The sources of the first FET and the fourth FET are connected to the input of the first inverter, and the output of the first inverter is connected to the second FE.
T and the drain of the third FET, the sources of the second FET and the third FET are connected to the input of the second inverter,
The gate of the first FET is connected to the first clock, and the gate of the second FET
A semiconductor scanning circuit characterized in that a gate of an ET is connected to a second clock, and gates of a third FET and a fourth FET are connected to a control input.