JPS6382038A - Digital communication system - Google Patents

Abstract

PURPOSE:To make a free local communication by a communication system wherein plural stations or networks which are opposite in the type of the sign of binary information coexit by controlling the selecting operation of a sign inverting means so that the mismatching in sign between a transmission and a reception side to respective messages is complemented. CONSTITUTION:A signal sent out of the transmission facility 1 of a transmission- side station A reaches the reception facililty 2 of a reception-side station B through an antenna 3a, a communication satellite 4, and then an antenna 3b. A sign inverting mechanism (equivalent NOT circuit) 5p or 6p is provided to either the transmission facility 1 of the station A or the reception facility 2 of the station B and this sign inverting mechanism is operated selectively so that the total number of equivalent NOT circuits between interface points alphaand beta is even or odd according to whether the signs of the stations A and B are opposite or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital communication system, and more particularly to a digital communication system in which stations having mutually opposite code types of binary information can be interconnected. .

[Conventional technology]

A typical digital communication system is designed with consideration in all respects for consistency among all the stations that make up the communication system. Therefore, in such communication systems, the correspondence between binary information and physical codes (eg, two different states in amplitude, phase, frequency, etc.) is constant. However, when heterogeneous networks are integrated or new networks are added, such as in satellite communication systems, VANs, etc., it is necessary to interconnect networks with different design concepts. In such a case, a measure is usually taken to ensure consistency only at the interface between the networks, and not to ensure consistency in the details of the system as a whole. Regarding codes, it is not specified how binary information and physical codes should be associated (for example, whether '1' and It ON+ should be expressed as large or small amplitudes, respectively), but simply the relationship between the timing clock and the timing clock. Only the code identification points in the relationship are defined. Such a strategy has the advantage of increasing the degree of freedom in the design of each component network and allowing optimal circuit design for each, but on the other hand, as described below, This will cause problems.

[Problem that the invention seeks to solve]

In a communication system in which only consistency at the interface point is ensured as described above, when a station A communicates with a station B that uses the same physical code, and when this station A communicates with a station B that uses the opposite physical code. A problem arises because there may be cases where the station C communicates with a station C that employs a code. For example, 61″
A station designed to be connected to a station that uses codes that represent ``1'' and ``0'' with large amplitude and small amplitude, respectively, is
If the signal is connected to a station that uses codes that represent small amplitude and large amplitude, respectively, the identification of binary information on the receiving side will be completely incorrect.

An object of the present invention is to solve the above-mentioned problems and to enable free communication between stations in a communication system in which stations that use mutually opposite code systems coexist.

[Means for solving problems]

According to the present invention, in a communication system in which stations that adopt mutually opposite code systems coexist, the code inversion means that is selectively activated is a transmitting unit of a station that can be a transmitting side or a receiving unit of a station that can be a receiving side. provided in at least one of the parts. This sign inverting means may be a negative circuit or a circuit that mutually switches the A line and the B line of the balanced mode signal line. Furthermore, the selective activation of the sign inverting means may be performed manually or automatically by detecting the encoding format of a predetermined binary information pattern.

[Effect]

The selective operation of said sign inverting means is controlled to compensate for the sign mismatch between the sender and receiver for each message. That is, if the code in the station functioning as the transmitting side and the code in the station functioning as the receiving side are the same, the sign inversion means is not activated, and if the signs in these stations are opposite to each other, Sign inversion means are activated to obtain sign alignment. In the case of one-station to one-station communication in which the partner station is specified in advance, the selective activation of the sign inverting means can be controlled manually, but in other cases, for example, in multi-station to multi-station communication, the selective activation can be controlled manually. Automated mechanisms can be adopted.

〔Example〕

FIG. 2 conceptually shows an example of a satellite communication system to which the present invention can be applied. For the sake of clarity, only the transmitting part of the station acting as transmitter and the receiving part of the station acting as receiver at a given time are shown. The signal sent from the transmitting equipment 1 of the transmitting station A is transmitted to the antenna 3a, the communication satellite 4,
The signal then passes through the antenna 3b and reaches the receiving equipment 2 of the receiving station B.

Transmission equipment 1 is an interface point α with computers, terminals, etc.
It consists of an encoder, a modulator, and other circuits provided between the antenna 3a and the antenna 3a, and the phase inversion effect that occurs in the waveform shaping, timing adjustment, amplification, etc. They are represented as negative circuits 5a to 5m. Further, the reception equipment flange 2 is a demodulator provided between the antenna 3b and the interface point β with a computer, a terminal, etc.

It consists of a decoder and other circuits, which also include n isometric negation circuits 6a to 6n similar to those in the transmission equipment 1. Note that, to simplify the explanation, it is assumed that binary information is encoded based on the magnitude of amplitude.

In such a communication path, the phase of the signal at the interface point β is the same as that at the interface point α, if the total number (m+n) of negative circuits between the interface point α and the same β is an even number. , if it is an odd number, it is in reverse phase. Therefore, the code at station A and the code at station B are of the same type (i.e. 11111, it
Q j# and the correspondence between large and small amplitudes are the same), then the total number of NOT circuits must be an even number. On the other hand, the code types at these stations are opposite to each other (i.e. 1” RQ
If the correspondence between u and the large and small amplitudes is mutually inverse), correct reproduction of binary information at station B is possible by setting the total number of NOT circuits to an odd number.

Figure 1 conceptually shows the present invention in correspondence with Figure 2.
Either one of the transmitting equipment 1 of station A or the receiving equipment 2 of station B is provided with an additional sign inversion mechanism (isometric negation circuit) 5p or 6P shown by a broken line in Fig. 1. Depending on the sign type at B, the interface point α and the same β
This sign-inverting mechanism is selectively activated such that the total number of isometric negation circuits between the transmitting equipment 1 is even or odd. Alternatively, it is sufficient if it is provided only on one side of the receiving equipment 2. However, in the actual equipment of each station, such a sign inversion mechanism may be provided in both the transmitting equipment and the receiving equipment. 3 shows an embodiment in which a negative circuit is provided in the receiving equipment 2 as a sign inversion mechanism 6p. An additional NOT circuit 6p' corresponding to the sign inverting mechanism 6p in FIG. , connect to the input of the line dry buffer. switch SW
The control in step 1 may be performed manually or automatically by circuits 9 to 15, as will be described later.

FIG. 4 shows an embodiment in which a balanced mode signal line switching circuit is provided in the receiving equipment 2 as the sign inverting mechanism 6p in FIG. When the interface between the transmitting equipment or receiving equipment and the computer, terminal, etc. is in balanced mode, the signal is
The signal is carried by a pair of signal lines called the line and the B line, and a line driver and a line receiver are placed at the sending and receiving ends, respectively. The output stage of the line driver and the input stage of the line receiver are both differential amplifiers, and the pair of inputs or the pair of outputs A and B are equal.

That is, even if outputs A and B of the line driver are connected to inputs A and B of the line receiver, respectively, or output A
Even if A and B are connected to inputs B and A, respectively, the operation of one circuit is guaranteed, but the relationship between the output of the line receiver and the combination of the values of the outputs A and B of the line driver is reversed.

Therefore, by switching the A line and the B line between the output point of the line driver and the input point of the line receiver,
The same result as inserting a negation circuit can be obtained.

In FIG. 4, the line driver buffer and its pair of output lines (A, B), resistors R1 to R3, and the line receiver 8 and its pair of input lines (A, B) constitute a balanced mode interface. Commercially available ICs can be used for the line driver buffer and line receiver 8. switch S
W2 and SWδ operate as a unit to switch the connection between the output lines A, B of the line driver buffer and the input lines A, B of the line receiver 8. That is, when these switches are on the contact V side, the output lines A and B of the line driver buffer are connected to the input lines A and B of the line receiver 8, respectively, creating a state in which no negative circuit is inserted, and these switches When is on the contact U side, the output lines A and B of the line driver buffer are connected to the input lines B and A of the line receiver 8, respectively,
A state in which a negative circuit is inserted appears. switch SWz
Similarly to the switch SWz, the control of the switch SW8 and the switch SW8 may be performed manually, or may be performed automatically by circuits 9 to 15, which will be described later.

For communication performed only between two stations specified in advance, switch SWz in FIG. 3 or switch SW in FIG.
z and SWa can be controlled manually. However, for example, TDM, which is often used in satellite communications,
A (Time Division Multiple
When multi-station to multi-station communication is performed, as in the Access) system, the forward/reverse relationship between the code types on the transmitting side and the receiving side changes dynamically. The switching of the switch is
It is necessary to perform this dynamically using an automatic mechanism. Circuits 9 to 15 in FIGS. 3 and 4 are provided for this purpose.

In FIG. 3, the well-known HDLC (High Le
It is assumed that the velData Link Control) procedure is adopted as the transmission procedure. 2 for HDLC procedure
In this case, a specific 8-bit pattern called a flag is set to ``0''.
1111110” are placed at the beginning and end of the frame.

Continuously inserted between frames.

The shift register 9 connected to the input line of the additional inverter 6p' has a length of 8 bits and functions as a serial-to-parallel converter for converting successive serial 8-bit inputs into parallel 8-bit outputs. Register 10 is.

The flag is fixedly held and the flag pattern is supplied as an 8-bit parallel output. The first comparator 11 compares the parallel output of the shift register 9 with the parallel output of the register 10 and produces an output when they match. A second comparator 12 compares the parallel output of the shift register 9 with the parallel output of the register 10 via an 8-bit wide NOT circuit 13, and produces an output when they match. Therefore, the first comparator 11, when the input bit string of the NOT circuit 62' is equal to the flag pattern "01111110",
When the last bit arrives, the second comparator 12 generates an output, indicating that the input bit string is the negation of the flag pattern.
10000001''' produces an output when the last bit arrives. The output of the first comparator 11 sets a flip-flop 14, and the output of the second comparator 12 sets this flip-flop 14. The set side output 15 of the flip-flop 14 holds the switch SWl at the contact V side while it is at the on level, and holds the switch SWz at the contact U side while it is at the off level. Therefore, as long as flags with normal signs continue to appear at the input of the negation circuit 6 p / at the beginning and end of the frame and between frames.

The flip-flop 14 is kept set by the output of the first comparator 11 and the additional NOT circuit 6p' is bypassed. On the other hand, for example, when a flag with an inverted sign appears at the beginning of a frame or between frames, the flip-flop 14 is reset by the output of the second comparator 12, and the additional NOT circuit 6p
' is inserted into the circuit and this state is maintained until a flag with a correct sign appears.

The configuration and operation of circuits 9 to 15 in FIG. 4 are the same as in FIG. 3, except that signal 15 simultaneously controls the pair of switches SW2 and SWa, and detailed explanation thereof will be omitted.

3 and 4, except that even when a specific bit pattern for identifying the header part of a frame is used instead of a flag in the HDLC procedure, this specific bit pattern is set in the register 10. , no essential changes to circuits 9 to 15 are required.

〔Effect of the invention〕

According to the present invention, in a communication system in which a plurality of stations or networks with mutually opposite sign types of binary information coexist,
Free communication between any two stations or multiple stations is enabled by a simple mechanism, which facilitates integration of disparate networks and new additions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram conceptually showing the present invention applied to a satellite communication system, FIG. 2 is a block diagram of a conventional satellite communication system, and FIGS. 3 and 4 are reception diagrams in the communication system according to the present invention. 3 is a block diagram showing first and second examples of the section. l...Transmission equipment, 2...Reception equipment, 3a, 3b...
・Antenna, 4...Communication satellite, 58~5m, 6a~6
n... Equivalent negation circuit inherent in each equipment, 5P+62.
. . . Selectively created sign inversion means, 6p' . . . Added negation circuit, 7 . . . Line driver, 8 . .
Line receiver, SWl...Switch for selectively activating an additional negative circuit, sw, sw,...A
Switches for selectively switching line and B line, 9-15
. . . A circuit that determines the code type of a specific code pattern and controls SWl or SW.

Claims (1)

[Claims] 1. A plurality of stations in which binary information is represented by a first physical code, and a second station in which the correspondence between the binary information and the physical state is opposite to that of the first physical code. It includes at least one station in which binary information is represented by a physical code, these stations can be selectively interconnected, and at least a transmitter of a potential transmitter and a receiver of a potential receiver. A digital communication system having sign inversion means, one of which is selectively activated. 2. In claim 1, a receiving unit of a station that can be a receiving side comprises the code inverting means and a predetermined binary information pattern in the received signal represented by the first physical code. A digital communication system comprising: means for determining whether the code is represented by the second physical code; and means for selectively activating the sign inverting means in response to an output of the determining means. 3. In claim 2, the predetermined 2
The value information pattern is a flag in the HDLC procedure,
The selective actuation means is set to a first stable state when the flag represented by the first physical symbol is detected and the flag represented by the second physical symbol is set to a first stable state. A digital communication system including a bistable element that is set to a second stable state when detected. 4. The digital communication system according to claim 1, 2 or 3, wherein the sign inverting means is a negative circuit. 5. The digital communication system according to claim 1, 2, or 3, wherein the sign inverting means is means for mutually switching a pair of signal lines forming a balanced mode signal line.