JPS6380527A - Formation of compound semiconductor layer - Google Patents

Abstract

PURPOSE:To enable a compound semiconductor single crystal layer having a high quality to be formed efficiently in a relatively short period of time when the compound semiconductor layer is formed on a silicon (Si) substrate, by applying a thermal stress in the middle of the deposition process for improving the crystallinity of the deposited layer. CONSTITUTION:A GaAs layer 32 is first deposited on an Si substrate 31 in two steps until the thickness thereof reaches 2.6 mum without any temperature decreasing cycle. Then, in order to shorten the deposition stopping period, the thermal cycling is designed, for example, such that the initial temperature decreasing rate is about 2 deg.C/second; the lower limit of themperature is 300 deg.C; and the higher limit is 700 deg.C. Ten thermal cycles consisting of such temperature increasing and decreasing cycles are carried out for each 0.1 mum thickness of a deposited layer so that a thermal cycle layer 33 having a thickness of 1.0 mum is formed at a position spaced by 1.3 mum or over in the direction of deposition from the interface between the silicon substrate 31 and the GaAs layer 32. Further, a 1.0 mum thick GaAs layer 34 is deposited at a deposition temperature of 700 deg.C. Thus, by performing the thermal cycle deposition process at a position spaced by 1.3 mum or over in the deposition direction from the interface between the silicon substrate 1 and the GaAs layer 2, the dislocation density can be decreased by ten times or more in comparison with conventional methods.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method for forming a compound semiconductor layer, and particularly to a method for forming a high quality compound semiconductor layer on a silicon substrate using a silicon substrate. It is.

<Prior Art> Compound semiconductors such as GaAs and InP are being utilized for high-performance and highly functional devices by taking advantage of their excellent characteristics. However, compound semiconductor crystals are generally expensive, and problems such as difficulty in obtaining large-area, high-quality substrate crystals remain unsolved. In an attempt to overcome these problems, we used cheap, high-quality, and lightweight silicon as a substrate, stacked compound semiconductor layers on this silicon substrate, and then constructed the aforementioned devices on the stacked compound semiconductor layers. Attempts have been made to manufacture semiconductor devices.

Although several methods for manufacturing compound semiconductor devices using such silicon substrates have been proposed, they are still inferior to bulk crystals in terms of crystal quality and the like.

For example, the following methods are currently being attempted to form a single crystal GaAs layer on a silicon (Si) substrate.

That is, when forming a GaAs layer on a silicon (Si) substrate, it is a so-called two-step growth method in which a preliminary deposition layer is formed in advance, and then GaAs is epitaxially grown under normal growth conditions. As the predeposition layer, a GaAs layer+Ge layer formed at a lower temperature than normal growth conditions, or a buffer layer formed by alternately laminating GaP and GaAs, or the like is used.

As an example of this, a growth process using a two-step growth method using a GaAs layer as a preliminary deposition layer will be described below.

First, MOCVD or M
Approximately 10OA of Ga at a temperature below 450℃ using the BE method
After forming an As layer, the temperature of the substrate is raised to a normal GaAs epitaxial growth temperature (600° C. to 750° C.), and then a GaAs layer is grown.

FIG. 3 is a schematic diagram showing the structure of a GaAs layer 2 on a silicon (Si) substrate 1 obtained by a two-step growth method, and 3 is a preliminary deposited layer.

When any of the above-mentioned materials is used as the preliminary deposit layer 3, a high density of mismatched dislocations occurs in the interface region between Sl and GaAs due to the difference in lattice constants between Si and GaAs (~4%), and one of them The part propagates in the growth direction during growth and penetrates the growth layer. In particular, the stress caused by the large difference in expansion coefficient between the silicon (Si) substrate 1 and the GaAs layer 2 during cooling from the growth temperature to room temperature after the completion of growth greatly promotes the propagation of dislocations in the growth direction, so dislocations are generated near the surface. When reaching the active layer formation region and manufacturing a device on the GaAs layer 2, the device performance is most affected.

The density of mismatched dislocations generated in the interface region between Si and GaAs is about 10 cm, and the density of dislocations that have reached the GaAs surface after stacking 3 Am of GaAs is about 10 cm.
cm was determined by transmission electron microscopy (TEM) observation and etch pitch density (EPD) using molten KOH.
) is known from the measurement results. Dislocations act as recombination centers for minority carriers, causing a significant decrease in minority carrier lifetime in crystals with high density dislocations. Therefore, the performance of a compound semiconductor device using minority carriers is significantly degraded.

As a method to reduce this high-density dislocation, Zaul (T
proposed a combined method of growth interruption and thermal cycling (thermal cycle growth method) (16th, IEEE
PVSC, 1982).

FIG. 4 is a diagram showing an example of a temperature program based on this thermal cycle growth method. In addition, FIGS. 5(A) to (Q) are diagrams for explaining one cycle of this thermal cycle growth method. 5(4) shows that some of the dislocations existing in the predeposited layer 3 have reached the GaAs layer 21, and the substrate temperature increases during the subsequent interruption of growth shown in CB) of the same figure. They claim that the temperature is lowered from 700°C to room temperature, and dislocation loops are formed due to interactions between dislocations, and dislocations are reduced in the subsequent second growth layer 22 (FIG. 5 (0)). Figure 5 (A) to (C)
The dislocation reduction effect was confirmed only after repeating the process shown in 10 times or more.

<Problems to be Solved by the Invention> However, when the above conventionally proposed process is actually applied to manufacturing, the growth layer formed by repeated thermal cycles (hereinafter referred to as the thermal cycle layer) is Until now, it has not been clarified where to form a compound semiconductor growth layer on a silicon (Si) substrate to efficiently obtain a high-quality active layer. A thermal cycle layer is immediately formed from the interface between the compound semiconductor layer and the compound semiconductor layer. 2 times
However, in this case, there was a manufacturing problem in that the time required for thermal cycle growth was significantly increased. That is, for example, when using a metal organic chemical vapor deposition (MOCVD) method using a high-frequency heating/water-cooling reaction tube method, which is said to have relatively short heating and cooling times, The time required to form a GaAs growth layer of about 3 μm is about 1 hour, but the time required to perform 20 thermal cycles is more than 12 hours, which is a great improvement in terms of time efficiency. There is a manufacturing issue.

The present invention was created in view of the above points, and is an improved method that solves the problems of the thermal cycle growth method for increasing the quality of the grown layer when growing a compound semiconductor layer on a silicon substrate. The purpose of this invention is to provide a novel method for forming a compound semiconductor layer.

Means and operation for solving the above problems> In order to achieve the above object, the method for forming a compound semiconductor layer of the present invention includes the following steps:
A first growth step in which the compound semiconductor layer is continuously grown without a temperature cooling cycle, a step in which the growth of the compound semiconductor layer is interrupted during the growth of the compound semiconductor layer following this first growth step, and a step in which the temperature of the growth wafer is adjusted. and a second growth step consisting of a cooling step of lowering the temperature to a temperature lower than that temperature, and the second growth step is performed at a distance of more than 1.3 μm in the growth direction from the interface between the silicon substrate and the compound semiconductor layer. At least try to do it.

That is, the present invention is a method for forming a compound semiconductor layer on a silicon (Si) substrate, and can reduce the propagation of mismatched dislocations existing between the substrate and the compound semiconductor layer and dislocations caused by thermal stress in a shorter time than in conventional methods. Efficiently confined near the interface,
By reducing the number of dislocations in the active layer formation region of the upper compound semiconductor device, it is possible to provide a compound semiconductor device that can be of high quality, low cost, and lightweight, and the present invention The method of improving the crystallinity of a grown layer by applying thermal stress during growth, which is used in the following, can be understood as follows.

That is, since the generation and propagation of dislocations are promoted by local stress concentration, thermal stress based on the difference in thermal expansion coefficient between the silicon (Si) substrate and the GaAs layer is applied to the grown layer during cooling after the growth is interrupted. The dislocations near the pre-deposited layer are propagated to the surface of the crystal layer and release part of the thermal stress in the crystal.

When the temperature is raised again, the second GaAs layer is grown, and then the temperature is lowered, the dislocations in the first grown layer mutually form a loop, or point defects due to impurities present in the grown layer are fixed on the dislocations. This prevents the propagation of dislocations (this is called immobilization of dislocations). In this way, the dislocation density propagating to the second grown layer can be reduced compared to that in the first layer.

Therefore, by repeating the forced formation of dislocation loops by applying thermal stress to the growing layer when the temperature is lowered, and the immobilization of dislocations by reducing the thermal stress when the temperature is rising, the number of dislocations that reach the active layer region near the growing surface is reduced. It becomes possible to reduce the

Based on the above understanding, the present invention has been developed by selecting the formation position of the thermal cycle layer that is most effective for forming dislocation loops and immobilizing dislocations by forcibly introducing dislocations, thereby efficiently growing silicon substrates in a relatively short period of time. This is intended to improve the quality of the compound semiconductor growth layer on the silicon substrate and enable it to be used as a substrate on which high-performance compound semiconductor devices can be manufactured. performing at least a thermal cycle growth method at a remote location;
It is characterized in that the distance from the interface between the silicon substrate and the compound semiconductor layer to the upper end of the thermal cycle layer is optimized by setting it to exceed 1.3 μm.

That is, the present invention has found that thermal cycle growth up to about 1.3 μm from the interface between the silicon substrate and the compound semiconductor layer hardly contributes to improvement of crystal quality. At least 1.3μ from the interface
By placing the upper end of the thermal cycle layer at a distance exceeding m, the quality of the compound semiconductor layer on the silicon substrate can be improved in a short time and efficiently.

<Examples> The present invention will be described in detail below based on Examples. Note that although the following examples describe the formation of a GaAs semiconductor layer, the present invention is not limited thereto;
The present invention can be similarly applied to the formation of other group (1) and (2) group compound semiconductor layers such as aP, InP, or mixed crystals such as GaInAs. Furthermore, the scope of application is not limited to the MOCVD method and the temperature of 700°C regarding the growth method and growth temperature; any method and temperature that allows compound semiconductor growth, such as the MBE method and halogen transport method, can be similarly applied. Needless to say, it is possible to do so.

Example 1 Two-step growth was performed by MOCVD using a high-frequency heating/water-cooled reaction tube.
Forming a GaAs layer of about 10 OA at a temperature of 50° C. or less,
After that, the usual GaAs epitaxial growth temperature (60
After raising the temperature of the substrate to 0°C to 750°C, a GaAs layer including a thermal cycle layer is grown, and the dislocation density near the surface of the grown layer is measured using planar TEM or EPD measurement method using molten KOH. evaluated.

As an example of applying the thermal cycle conditions of the present invention, as shown in FIG. 1, a GaAs layer 32 is first grown in two steps on a silicon (Sl) substrate 31 without a temperature cooling cycle.
The film was grown to a thickness of 6 μm, and then, in order to shorten the growth stop time, the lower limit temperature of the thermal cycle was set to 300°C, the initial cooling rate was approximately °C/sec, and the upper limit temperature was set to 700°C, and the growth layer thickness was A thermal cycle layer 33 with a thickness of 1.0 μm is formed from the interface between the silicon substrate 31 and the GaAs layer 32 by 1 step in the growth direction by performing 10 temperature-lowering/heating thermal cycles at intervals of 0.1 μm.
．． Formed at a distance of more than 3 μm, and an additional 1.0 μm
A GaAs layer 34 of 100 mL was laminated at a growth temperature of 700° C., and the dislocation density near the surface of the grown layer was measured.

Also, for comparison, the 6th
As shown in the figure, a GaAs layer 42 is first grown to a thickness of 0.1 μm on a silicon (Si) substrate 41 by two-step growth, and then the lower limit temperature of the thermal cycle is set to 90°C and the upper limit temperature is set to 700°C. ℃, and performed a thermal cycle of decreasing and increasing the temperature by lO psi for every 0.1 μm of growth layer thickness to form a thermal cycle layer 43 with a thickness of 1.0 μm, and then the silicon substrate 41
The distance from the interface between the GaAs layer 42 and the upper end of the thermal cycle layer 43 is 1.3 μm or less, and further 1.0 μm or less.
A μm thick GaAs layer 44 is laminated at a growth temperature of 700°C,
The dislocation density near the surface of the grown layer was measured. Table 1 is a comparison of the measured dislocation densities near the surface of the GaAs growth layer of the substrates having the structures shown in FIGS. 1 and 6 above.

Table 1 As is clear from Table 1, the dislocation density of sample (a), which was subjected to thermal cycles without selecting the optimum position, was 7.
．． 9X10 crn, the thermal cycle growth method according to the method of the present invention is applied to GaAs on silicon substrate 1.
It was carried out at a position beyond 1.3 μm in the growth direction from the interface of layer 2, and the distance to the top of thermal cycle layer 3 was 3.6 μm.
For sample (b) with μm, the dislocation density is 8.2X1
0cn1, and it was possible to reduce the dislocation density by about one order of magnitude compared to the conventional method.

Example 2 In Example 1 described above, the effect of reducing the dislocation density by the method of the present invention was demonstrated by changing the distance to the top of the thermal cycle layer. The thickness was fixed at 3 μm, and as shown in Figure 2,
First, an n-GaAs layer 52 was grown on an n-silicon (Si) substrate 51 in two steps to a thickness of 0.9 μm without a cooling cycle, and then under the same thermal cycle conditions as in Example 1. Every 0.1 μm growth layer thickness, 10 cycles total 1
．． Thermal cycle layer (n-GaAs layer) 53 with a film thickness of 0 μm
is grown, and further an n-GaAs layer 5 with a thickness of 0.8 μm is grown.
A p-GaAs layer 55 with a thickness of 4 and 0.3 Am was formed in this order, and an N-side electrode 56 and a P-side electrode 57 were formed on both ends. In this way, a junction with a depth of about 0.3 m (carrier concentration p
~2X101-'', n~lX10crn) The dark state current-voltage characteristics of the diode were measured.

For comparison, silicon (n-
3i) An n-GaAs layer 62 with a layer thickness of 0.3 μm is grown on the substrate 61 by two-step growth, and then an n-GaAs layer (thermal cycle layer) 63 with a layer thickness of 1.0 μm is completely grown. ,
Further, an n-GaAs layer 64 and a 0.00.
A p-GaAs layer 65 with a layer thickness of 3 μm is formed in this order,
Sample (b) with a structure in which an N-side electrode 66 and a P-side electrode 67 are formed at both ends, silicon (n-8i) as shown in FIG.
On the substrate 71, a layer of n-G was grown to a layer thickness of 27 μm in two steps.
An aAs layer 74 is formed, and p is deposited on it to a thickness of 0.3 μm
- Sample (c) with a structure in which a GaAs layer was formed and an N-side electrode 76 and a P-side electrode 77 were formed on both ends, and a sample (c) with a structure in which a GaAs layer was formed and an N-side electrode 76 and a P-side electrode 77 were formed, and a thermal cycle layer was subjected to 19 thermal cycles from the interface with the substrate, and The structure was a sample formed similarly to that shown in Figure 2 (
d) for each of
crn) The dark state current-voltage characteristics of the diode were measured.

Table 2 compares the measured values of saturation current of each of the samples described above.

Table 2 As is clear from Table 2, when comparing the saturation current values of each sample, the saturation current ( Io) = 1x1o A-what, which is almost the same as a diode that does not undergo thermal cycling (sample (C)), but the distance to the top of the thermal cycling layer is 1.9μ.
In the diode of sample (a) made according to the present invention, the diode of 0-1×lo-9A-i2 was reduced by about one order of magnitude, and this result shows that when using the growth layer grown according to the present invention, It is clear that the crystallinity of the active layer formed thereon is improved. Also, as in sample (d), the distance to the top of the thermal cycle layer is the same as in sample (a).
A diode with a thickness of 1.9 μm and subjected to 19 thermal cycle growth from the interface also had an IO value equal to that of diode (a). From these results, it is clear that thermal cycling up to approximately 1.3 μm from the interface hardly contributes to improvement of crystal quality, and thermal cycle growth is performed at a position beyond 1.3 μm in the growth direction from the substrate interface. It became clear that at least we could do it the way we did.

In this way, the thermal cycling layer is not formed near the 5i-GaAs interface, and the position of the thermal cycling layer is selected so that the upper end of the thermal cycling layer is at least 1.3 μm away from the interface. It has become possible to improve the quality of a GaAs layer on a silicon substrate efficiently in a short time.

Compound semiconductors formed on silicon (Si) substrates can be used as semiconductor substrates for various electronic devices and optical devices by improving their quality by reducing dislocation density using the method of the present invention. It shows excellent effects when formed to constitute a solar cell. That is, the light-receiving surface side can be formed using a GaAs layer or an InP layer with high photoelectric conversion efficiency, and the substrate supporting this compound semiconductor layer can be constructed using a relatively light and strong Si substrate, which increases efficiency. 5 A very advantageous solar cell in terms of weight can be obtained.

<Effects of the Invention> As described above, according to the present invention, a high quality compound semiconductor single crystal layer can be efficiently formed on a silicon (Si) substrate in a relatively short time compared to conventional methods. As a result, it can greatly contribute to lowering the cost and weight of compound semiconductor devices.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of the substrate structure for explaining one embodiment of the present invention, Fig. 2 is a schematic diagram of the substrate structure for explaining another embodiment of the invention, and Fig. 3 is a schematic diagram of the substrate structure for explaining another embodiment of the present invention. A schematic diagram of the substrate structure to explain the method for forming a compound semiconductor layer on the substrate. Figure 4 is a diagram showing an example of a temperature program based on the thermal cycle growth method. A schematic diagram for explaining the reduction in dislocation density, and FIGS. 6 to 8 are schematic diagrams showing sample structures for comparison with the method of the present invention, respectively. 31-・Silicon (Si) substrate, 32・=GaA
s layer, 33...GaAs thermal cycle layer, 34...
・GaAs layer. Agent: Patent Attorney Takeshi Sugiyama (and 1 other person) Figure 1 Figure 2 Figure 3 Figure 3 Figure 1', 4 Figure 5

Claims (1)

[Claims] 1. When growing a compound semiconductor layer on a silicon substrate, a first growth step in which the compound semiconductor layer is continuously grown without a temperature cooling cycle; The second growth step includes a step of interrupting the growth of the semiconductor layer in the middle of growth, and a temperature-lowering step of lowering the temperature of the growth wafer to below the growth temperature. A method for forming a compound semiconductor layer, characterized in that the step is performed at least at a distance of more than 1.3 μm in the growth direction from an interface of the semiconductor layer.