JPS6380323A - Bus driver for lsi - Google Patents

Abstract

PURPOSE:To remarkably improve the logic processing capability of an LSI by bringing an internal bus to a high level at a first half of a clock and driving plural bus drive circuits simultaneously at the latter half. CONSTITUTION:A P-channel transistor (TR) 2 is turned on at an L period being the 1st half of one period of a clock CK and the level of an internal bus 1 goes to H via a stray capacitance 3. An N-channel drive TR of function blocks 4, 5 is turned on during an H period of the clock CK at the latter half, each drive circuit of the blocks 4, 5 is driven simultaneously, the H level of the bus 1 is stored in a register 13 only when both contents of registers 11, 12 are logical 1, and the level of the bus 1 goes to L by any drive circuit connected to ground in order cases and the AND processing is applied by 2-step. This is the same as to OR, NAND, NOR processings thereby remarkably improving the logic processing function of the LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI, and particularly to a bus driver for an internal data bus that connects and transfers between a plurality of functional blocks.

[Conventional technology]

Conventionally, internal data buses are used in a time-sharing manner, and data is not output from bus drivers of two or more functional blocks at the same time.

An example of a conventional circuit is shown in FIG. 2(a). In fig.

1 is an internal data bus, 2 is a P-channel transistor, 3 is
Stray capacitance of rt internal data bus, 4, 5, 6°7rtL
Functional blocks composing 8I, 11 to 16 are registers that take in and output data in synchronization with the falling edge of CK;
1-23 are NOT circuits, 31-33.34-36.37
39 is a bus driver composed of N-channel transistors, and 41 is a logic operation circuit. As an example, consider a case where the data in the register 11 and the data in the register 12 are ANDed and the result is added to the register 13.

A timing chart at this time is shown in FIG. 2(b).

Operation ri.

1. Load the contents D1 of register 1 into register 14 via the internal data bus.

2. Load the contents D2 of the register 12 into the register 15 via the internal data bus.

3. Result D of performing an AND operation between the data in the register 14 and the data in the register 15 using the logic operation circuit 41
1 and D2 are taken into the register 16.

4. Load the contents of register 16, DI@D2, into register 13 via the data bus.

Here, the data transfer method will be explained using the case where the contents of the register 11 are transferred as an example.

First, when the clock CK is 101, the P-channel transistor 2 turns ON and becomes the internal data bus ri'l''.

Next, when the clock CK is 111, if the data in the register 11 is "II", both the N-channel transistor 33 and the P-channel transistor 2 are turned off. 1
If the data of 1 is 101 and BNl is 111, then
When the ON channel transistors 31 to 33 are all ON, the data bus becomes ri'0@.The contents of this internal data bus are stored in the register 14 in synchronization with the fall of the clock CK.
Transfer is possible by importing it into .

[Problem that the invention seeks to solve]

In the LSI with the conventional bus driver mentioned above,
In order to perform one AND operation, it is necessary to perform 5 steps of processing as shown in Figure 2 fb), and the LS
It has the disadvantage of deteriorating the processing capacity of I.

[Means for solving problems]

The bus driver of the present invention is a circuit that sets an internal data bus to a high level in the first half of one clock cycle.

It has a plurality of bus drivers that output data under the control of a control signal for outputting data to an internal data bus in the second half of a clock cycle, and has two or more bus drivers in an output state at the same time. By doing so, AND or r! at the same time as the transfer! It has a function to perform OR operation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Figure 1! a) r; is a circuit diagram showing an embodiment of the present invention;

In the figure, the lri internal data bus, 2rip channel transistors, 3 the stray capacitance of the internal data bus, 4, 5
．． Functional blocks that make up 6rtLsI.

11 to 13A register that takes in and outputs data in synchronization with the fall of riCK, 21.22 is a NOT circuit, 31
33. 34 to 36 are bus drivers composed of N-channel transistors.

Similar to the explanation of the prior art, an AND operation is performed on the data in register 11 and the data in register 12, and the result is stored in register 1.
Let us consider the case of incorporating into 3. A timing chart at this time is shown in FIG. 1(b).

In the present invention, bus drivers 31 to 33 differ from the prior art.
By setting the bus drivers 34 to 36 to the output state at the same time, the internal data bus can be set to 111 only when the data in register 1 and the data in register 2 are both 111. That is, an AND operation can be performed. It can be seen that by loading this result into the register 13, the transfer and AND operation processing described in the description of the prior art can be realized using the circuit of the present invention.

〔Effect of the invention〕

As explained above, the bus driver of the present invention can simultaneously perform data transfer and AND operation by transmitting data from two blocks at the same time.

When performing an AND operation between register data and transferring it to another register.

Conventionally, five steps were required, but according to the present invention, only two steps are required (the processing capacity of the LSI can be greatly improved).

Here, we have explained the AND operation, but similarly, N
AND operations, NO operations, etc. are also possible. Furthermore, it is also possible to perform logical operations between three pieces of data by setting three or more bus drivers to the output state at the same time.

[Brief explanation of the drawing]

Fig. 1 fa), fb) ri shows an embodiment of the present invention, talri its circuit diagram, fb) ri (a) operation typing chart, Fig. 2 (a), fb) shows an example of the conventional embodiment (a) is its circuit diagram, (b) rtt
It is a timing chart showing the operation of a+. CK...Clock, EN, BNI~WN3...
... Bus driver control signal %l ... Internal data bus, 2 ... P-channel transistor, 3 ... Stray capacitance, 4 to 7 ...・Functional blocks, 11 to 16...Registers, 21 to 23
......NOT circuit, 31 to 39...Bus consisting of N-channel transistors (α Lugis 73)

Claims (1)

[Claims] In a bus driver for an internal data bus that transfers signals between a plurality of functional blocks constituting an LSI in synchronization with a clock signal, a circuit that sets the internal data bus to a high level during the first half of one cycle of the clock signal; N bus drive circuits that output data to the internal data bus under control of a control signal for outputting data to the internal data bus in the latter half of one cycle of the clock signal; A bus driver characterized in that an AND or OR operation is performed by simultaneously putting M bus drive circuits into an output state.