JPH1027050A - Serial transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output data as they are without logically repeating and outputting data by software of a CPU, and to prevent error in software design by connecting a drive output CPU and a peripheral device through a diode. SOLUTION: A CPU 1 has an output buffer 11 and an input buffer 12. A CPU 2 has an output buffer 21 and an input buffer 22. Further, the peripheral device 3 has an open-collector output transistor 31 and an input buffer 32. The peripheral device 4 has an open-drain output FET 41 and an input buffer 42. Then a diode 6 has its cathode side connected to the drive output port A of the CPU 1 and its anode side connected to a serial data bus 10 for bidirectional semi-duplex communication. Further, a diode 7 has its cathode side connected to the drive output port E of the CPU 2 and its anode side connected to a serial bus 10. Further, a resistance 5 pulls up the serial data bus 10 to a power input terminal W.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial transmission system, and more particularly to a serial transmission system in data communication between logical devices having different output formats.

[0002]

2. Description of the Related Art A serial interface circuit of a microcomputer according to the first prior art is disclosed in
266645, "Serial interface circuit"
Referring to FIG. 3, there is provided a serial signal input / output terminal 108 provided inside a microcomputer 112 and directly connected to a serial data bus 109, an input buffer 101, an arbitrary bit shift register, and a serial input / output terminal. The serial transfer means 104 inputs the signal 102 as shift data in synchronization with the shift clock 103, shifts the shift register, and outputs the output of the last stage of the shift register as a serial output signal 105, and the serial output signal 105 is connected to the gate. It is composed of a MOS-type FET 106 which is inputted and whose source is grounded and whose drain is connected to the input / output terminal 108 and the input buffer 101. The serial data bus 109 connected to the serial signal input / output terminal 108 is pulled up by the resistor 110 and the second potential 111.

[0003] First, the operation when serial transmission is performed will be described.

When the serial output signal 105 output from the serial transfer means 104 in synchronization with the shift lock 103 based on the serial transfer information is at "H" level, the MOS
The type FET 106 becomes conductive, and the first potential 107 (GND level in this example) is output from the serial signal input / output terminal 108 to the serial data bus 109. At this time, the input buffer 101 is connected to the serial signal input / output terminal 1
A first potential 107, which is a potential 08, is input as the serial input signal 102, and the serial transfer unit 1044 synchronizes the serial input signal 102
Take in. When the serial output signal 105 is at "L" level, the MOS FET 106 is turned off,
Although the serial signal input / output terminal 108 is in an input state, since the serial data bus 109 is connected to the second potential 111 (power level in this example) via the resistor 110, the serial data bus 109 and the serial signal The output terminal 108 has the second potential 111.

At this time, the input buffer 101 inputs the second potential 111 from the serial signal input / output terminal 108 as the serial input signal 102, and
04 fetches the serial input signal 102 in synchronization with the shift clock 103.

Next, the operation for performing serial reception will be described.

In this case, serial transfer information is set in the serial transfer means 104 so that the serial output signal 105 is always at "L" level. As a result, during serial reception, the MOS FET 106 is always in a non-conductive state, and the serial signal input / output terminal 108 is always in an input state, so that signals do not collide on the serial data bus 109 and the input buffer 101 The transmitted signal is input as a serial input signal 102 from a serial signal input / output terminal 108 via a bus 109, and a serial transfer unit 104 captures the serial input signal in synchronization with the shift clock 103.

Next, in a serial transmission system according to a second prior art to which the "serial interface circuit" disclosed in Japanese Patent Laid-Open No. 62-266645 is applied, referring to FIG. When half-duplex bidirectional communication is performed through a single serial data bus between devices, the input ports B, F, K, and Q of each device are connected to the serial data bus 10 as they are. Connected, and the output of each device is the open collector of transistor 31 and FET4
1, the output of the open drain is directly connected to the serial data bus 10, and the drive output of the output buffer 11 and the output buffer 21 is connected to the serial data bus 10 via each of the FET8 and the FET9.

[0009]

The first problem is that, in these conventional serial transmission schemes, when the drive output of the microcomputer is connected to the serial data bus, the logic is inverted and the software is inverted. There was a problem that it caused a design error.

The reason is that the logic is inverted in the FET connected to the drive output of each microcomputer.

A second problem is that, in the configuration of the conventional serial transmission system, in order to connect a device which does not have a logical inversion function and has only a drive output to a serial data bus, the logic shown in FIG. So that the inversion circuit 20
Had to be added.

The reason is that, for example, when the FET 8 is directly connected to the output of the output buffer 11 of the CPU 1 in FIG.
Data at output port A and serial data bus 10
The logic with the above data is inverted, and communication with other devices, that is, the CPU 2 and the peripheral devices 3 and 4 cannot be performed. On the other hand, the addition of the inverting circuit 20 increases the number of parts, the cost of components, and the mounting area. Because it becomes.

[0013]

According to the serial transmission method of the present invention, a cathode side of a diode is connected to a drive output port of a first device such as a CPU having no open collector output or open drain output, and an anode of the diode is connected to the drive output port. Side to a common serial data bus for two-way half-duplex communication.
Connecting a plurality of input ports of the device to the serial data bus to the serial data bus,
Between a plurality of devices having the drive output,
Performs bidirectional half-duplex serial transmission.

In the serial transmission system according to the present invention, at least one open collector output of a second device such as a peripheral device having an open collector output and one or more input ports of the second device are connected to the serial data bus. Bidirectional half-duplex serial transmission is performed between a plurality of first devices such as CPUs having the drive outputs and second devices such as the peripheral devices having one or more open collector outputs.

Further, the serial transmission system according to the present invention
An open drain output of a third device, such as a peripheral device having an open drain output, and one or more input ports of the third device are connected to the serial data bus, and a plurality of the first devices having the drive output are connected. Bidirectional half-duplex serial transmission is performed between this device and a third device such as the peripheral device having one or more open drain outputs.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1 showing one embodiment of the present invention, the serial transmission system includes a CPU 1 having an output buffer 11 and an input buffer 12, a CPU 2 having an output buffer 21 and an input buffer 22, and an open collector output. Transistor 31 and input buffer 32
Peripheral device 3 having an open drain output F
A peripheral device 4 having an ET 41 and an input buffer 42 and a serial data bus 10 for bidirectional anti-duplex communication
And a diode 6 in which the cathode side is connected to the drive output port A of the CPU 1 and the anode side is connected to the serial data bus 10, and the cathode side is connected to the drive output port E of the CPU 2 and the anode side is connected to the serial data bus 10. It comprises a diode 7 and a resistor 5 for pulling up the serial data bus 10 to the power input terminal W.

Here, CPU1 and CPU2 are TTL level output and TTL level input, peripheral device 3 is open collector output and TTL level input, and peripheral device 4 is open drain output and TTL level input.

Next, the operation will be described with reference to FIG. 1 and FIG. The format of data to be communicated on the serial data bus 10 is start-stop synchronization, and has an 11-bit configuration of ST + D0 to D7 + P + SP always at "H" level. As shown in FIG. 2, ST is a start bit (= "L").
Level), D0 to D7 are 8-bit data, P is parity, SP is stop bit (= “H” level), and S
Start data at T = “L” level, then 8bi
Assuming that t is data and P is parity, SP = "H" is the end of data. Here, P is a parity bit which determines even parity / odd parity / parity ignoring or the like depending on the system to be realized. Here, each of the buffers, CPU1, CPU2, and peripheral devices 3 and 4 in FIG. 1 always output "H" level when not performing data communication and when receiving data, that is, always. Shall be. When the CPU 1 and the CPU 2 output “H” level, they are connected to the serial data bus 10 through the diode 6 as a pseudo open collector (or open drain). Since the peripheral device 3 is an open collector output, when it outputs an "H" level, it is opened. When the peripheral device 4 is also an open drain, it outputs an "H" level and becomes open, and is connected to the serial data bus 10. At this time, the serial data bus 10 is pulled up to the power supply voltage via the power supply input terminal W by the resistor 5 and becomes "H" level.

Here, when data is transmitted from the CPU 1, first, the level of the input port B is checked to confirm that all the other devices are outputting the "H" level. If the input port B is at the "H" level, the serial data bus 10 is considered to be free, and FIG.
Is output from the output port A in the format of
At this time, the CPU 1 receives its own output data from the input port B simultaneously with the data output, and monitors the data internally. When the data output is completed, the CPU 1 checks whether the output data and the data input to the monitor are the same,
If they are the same, it is considered that the data transmission has been performed reliably.
J is determined to be G (impossible). The processing after the transmission NG is defined between the devices, and the description is omitted here. Further, data transmission by the CPU 2, the peripheral device 3 or the peripheral device 4 is performed in the same manner.

Next, the data receiving operation of the CPU 1 is performed by detecting the falling transition point from the "H" level to the "L" level at the input port B, and using this as the start of data, the data in the format of FIG. Receive. Also, C
Data reception by the PU 2, the peripheral device 3, and the peripheral device 4 is performed in the same manner.

As described above, a drive output CPU and peripheral devices conventionally connected to a serial data bus via FETs, transistors or open drain output logic elements are now connected via a diode. Logical inversion of the output port of the CPU does not occur, and two components including an inversion circuit and an FET when a device having only a drive output is connected can be reduced to one diode.

[0023]

A first effect of the present invention is to perform communication by connecting a device having no open-drain output to a serial data bus having an open-drain wired-OR configuration without inverting the output of the device. It is possible to do. As a result, the data can be output as it is without logically inverting and outputting the data by software such as a CPU, and a software design error can be prevented.

The reason for this is that a pseudo open drain is realized by using a diode that does not cause logical inversion in the drive output of the device.

Next, the second effect according to the present invention can be realized by connecting a device without a logical inversion function to a serial data bus having an open-drain wired-OR configuration through one diode. That's it. As a result, it is possible to reduce the number of parts, member costs, mounting area, and the like.

The reason for this is that a single diode is used instead of two components, which are a device for logic inversion and an FET for forming an open drain.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a serial transmission system according to one embodiment of the present invention.

FIG. 2 is an example of a data format on a serial bus according to the embodiment.

FIG. 3 is a circuit diagram showing a first conventional example.

FIG. 4 is a circuit diagram showing a second conventional example.

FIG. 5 is a circuit configuration example in which a logical inversion circuit is added to the configuration of the second conventional example.

[Explanation of symbols]

 Reference Signs List 1 CPU 2 CPU 3 Peripheral device 4 Peripheral device 5 Resistance 6 Diode 7 Diode 10 Serial data bus 11 Output buffer 12 Input buffer 21 Output buffer 22 Input buffer 31 Transistor 32 Input buffer 41 FET 42 Input buffer A Drive output port B Input port E Drive output port F input port J output port K input port P output port Q input port W ~ Z power input terminal

Claims (3)

[Claims] 1. A bidirectional half-duplex communication serial device in which the cathode side of a diode is connected to the drive output port of a first device such as a CPU having no open collector output or open drain output, and the anode side of the diode is common. A plurality of components connected to the data bus and connected to the serial data bus such as an input port of a first device such as the CPU are connected to the serial data bus. And a bidirectional half-duplex serial data transmission. 2. A plurality of devices having an open collector output, wherein one or more open collector outputs of a second device such as a peripheral device and an input port of the second device are connected to the serial data bus, and A bidirectional half-duplex serial data transmission between a first device such as CPUs and a second device such as the peripheral device having one or more open collector outputs. . 3. A plurality of drive devices having the drive output by connecting at least one open drain output of a third device such as a peripheral device having an open drain output and an input port of the third device to the serial data bus. A bidirectional half-duplex serial data transmission between said first devices and a third device such as said peripheral device having said one or more open drain outputs.