JPS6379379A - Manufacture of self-alignment type thin film transistor - Google Patents
Manufacture of self-alignment type thin film transistorInfo
- Publication number
- JPS6379379A JPS6379379A JP61224729A JP22472986A JPS6379379A JP S6379379 A JPS6379379 A JP S6379379A JP 61224729 A JP61224729 A JP 61224729A JP 22472986 A JP22472986 A JP 22472986A JP S6379379 A JPS6379379 A JP S6379379A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- photoresist layer
- self
- photoresist
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000010408 film Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000007796 conventional method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
この発明は、半透明動作半導体膜を用いて自己整合型薄
膜トランジスタを製作するのに、不透明ゲートとの自己
整合パターン形成に長時間を要するという問題を解決す
るために、露光バターニング用のフォトレジストを厚い
第１の層と薄い第２の層に分割し、第１層は予め上部よ
り露光し、背面露光を第２の層で行い、露光時間の短縮
を可能とする。[Detailed Description of the Invention] [Summary] The present invention solves the problem that it takes a long time to form a self-aligned pattern with an opaque gate when manufacturing a self-aligned thin film transistor using a semi-transparent operating semiconductor film. In order to reduce the exposure time, the photoresist for exposure patterning is divided into a thick first layer and a thin second layer, and the first layer is exposed from the top in advance and the second layer is exposed from the back. is possible.
この発明は液晶あるいは、エレクトロルミネッセンス等
の駆動に用いる薄膜トランジスタの製造方法に関するも
のである。The present invention relates to a method for manufacturing a thin film transistor used for driving liquid crystals, electroluminescence, etc.
薄膜トランジスタは、素子を微細化するためにゲート電
極（合圧）をフォトマスクとして用いる自己整合型の薄
膜トランジスタが開発されている。In order to miniaturize elements, self-aligned thin film transistors have been developed that use a gate electrode (combined pressure) as a photomask.
しかしながら、薄膜トランジスタは動作半導体層として
一般に水素原子を添加したアモルファス・シリコン（以
後ａ−５ｉ：Ｈと記す）等の半透明材料を多く用いてい
る。この動作半導体層が半透明であることから、背面露
光で薄膜トランジスタを製作しようとすると、露光に長
時間を要すると云う不都合があり、これを解決する製造
方法が必要とされている。However, thin film transistors generally use semitransparent materials such as amorphous silicon (hereinafter referred to as a-5i:H) doped with hydrogen atoms as an active semiconductor layer. Since this active semiconductor layer is semi-transparent, if a thin film transistor is manufactured by back exposure, there is a disadvantage that exposure takes a long time, and there is a need for a manufacturing method that solves this problem.
第３図は従来の自己整合型の薄膜トランジスタの製造工
程図である。まず第２図（ａ）の工程において、透明基
板、例えばガラス基板１上にクローム（Ｃｒ）からなる
不透明のゲート電極２をパターニングし、その上部に、
シラン（５ｉｔｂ ）をベースガスとしてプラズマＣＶ
Ｄ （以後Ｐ−ＣＶＤと記す）法にて３００ｎｎ厚さの
ゲート絶縁膜となる窒化シリコン（ＳｉＮ）膜３と、半
透明動作半導体膜となる１１００ｎのａ−Ｓｉ ： Ｈ
膜４を被着形成する。FIG. 3 is a manufacturing process diagram of a conventional self-aligned thin film transistor. First, in the process shown in FIG. 2(a), an opaque gate electrode 2 made of chrome (Cr) is patterned on a transparent substrate, for example, a glass substrate 1, and on the top thereof,
Plasma CV using silane (5 itb) as base gas
D (hereinafter referred to as P-CVD) method: Silicon nitride (SiN) film 3 that becomes a gate insulating film with a thickness of 300 nm and a-Si film of 1100 nm that becomes a semi-transparent operating semiconductor film: H
A film 4 is deposited.
次ぎに第３図（ｂｌの工程で、その上部にフォトレジス
ト（マイクロポジット社製１４００−２７）を厚さ１゜
５μｍスピンコードしてフォトレジスト層５を形成する
。この形成した後にガラス基板１の側から紫外光１１を
照射してフォトレジスト層５に対するゲート電極２をマ
スクとするの背面露光を施す。Next, in the step shown in FIG. 3 (bl), a photoresist (1400-27 manufactured by Microposit Co., Ltd.) is spin-coated on top of the photoresist layer 5 to a thickness of 1.5 μm. After this formation, the glass substrate 1 Ultraviolet light 11 is irradiated from the side to expose the back surface of the photoresist layer 5 using the gate electrode 2 as a mask.
この場合ａ−３ｉ：Ｈ膜４が半透明、かつ１１００ｎの
ＦＫさであるためにフォトレジストＦｉ５に到達する光
量は、１００分の１以下となり、フォトレジスト層を十
分露光するためには、１００倍以上の時間を要すること
となる。この露光時間は数十分〜数時間の長時間必要と
される。この背面露光によって、フォトレジスト層５に
はゲート電極に自己整合して未露光部が生じる。In this case, since the a-3i:H film 4 is semitransparent and has an FK of 1100n, the amount of light reaching the photoresist Fi5 is less than 1/100, and in order to sufficiently expose the photoresist layer, the amount of light reaching the photoresist Fi5 is less than 1/100. It will take more than twice as long. This exposure time is required for a long time from several tens of minutes to several hours. By this back exposure, an unexposed portion is generated in the photoresist layer 5 in self-alignment with the gate electrode.
次に第３図（Ｃ）の工程で現像を行うと、前記未露光部
に対応したフォトレジスト層の自己整合パターン゛５′
が形成される。なお、このパターンは上記露光時に紫外
光１１の散乱によって端部が露光されるので、そのパタ
ーン幅はマスクとして用いたゲート電極２の幅より０．
１〜１μｍ狭く形成される。Next, when development is carried out in the step shown in FIG.
is formed. Note that since the edges of this pattern are exposed by scattering of the ultraviolet light 11 during the exposure, the pattern width is 0.0 mm wider than the width of the gate electrode 2 used as a mask.
It is formed 1 to 1 μm narrower.
次ぎに、第３図（ｄ）の工程で自己整合パターン５′の
上部に厚さ５０ｎｍのｎ” ａ−Ｓｔ：）ＩＩＱからな
るドープ半導体膜６を１２０℃のＰ−ＣＶＤ法で成形し
、さらにその上含むａ−Ｓｉ：！（膜４上にチタン（Ｔ
ｉ）膜７を真空蒸着法で１１００ｎ厚に形成する。Next, in the step shown in FIG. 3(d), a 50 nm thick doped semiconductor film 6 made of n''a-St:)IIQ is formed on the self-aligned pattern 5' by P-CVD at 120°C. Furthermore, it contains a-Si:!(titanium (T) on the film 4).
i) Form the film 7 to a thickness of 1100 nm by vacuum evaporation.
次に第３図（ｅｌの工程で前記自己整合パターン５′上
の材料、ｎ ” ａ−Ｓｉ：Ｈ膜６とＴｉ膜７をリフト
オフ法によって除去し、さらに素子分離工程やＴｉ膜の
エツチング工程を経て薄膜トランジスタ素子が得られる
。なお図中りとＳはドープ半導体膜６とＴｉ膜７との積
層構造よりなるソース１掻とドレイン電極を示す。Next, in the process shown in FIG. Through these steps, a thin film transistor element is obtained. In the figure, reference characters 1 and S indicate the source 1 and drain electrodes each having a laminated structure of a doped semiconductor film 6 and a Ti film 7.
前記した従来の自己整合型の薄膜トランジスタの製造方
法は、半透明の動作半導体膜を介してフォトレジスト層
を基板背面から露光し自己整合パターンを作成するため
に、背面露光に長時開票するという問題があった。The above-mentioned conventional method for manufacturing self-aligned thin film transistors has the problem of requiring long back exposure to create a self-aligned pattern by exposing the photoresist layer from the back side of the substrate through a semi-transparent active semiconductor film. was there.
この発明は、以上のような従来の状況から背面露光の時
間の短縮の図れる薄膜トランジスタの製造方法の提供を
目的とするものである。The object of the present invention is to provide a method for manufacturing a thin film transistor that can shorten the time required for back exposure in view of the conventional situation as described above.
この発明では、第１図に示すようにフォトレジスト層を
５−１ と５−２との２層構造とし寂に形成した厚い第
１のフォトレジスト層５−１は、同図（ａｌに示すよう
に基板１の上部から全面に紫外光１２−１を照射して露
光し、第２の紫外光に対し透明状態にして胃く。この後
それの上に移送した薄いフォトレジスト層５−２は同図
（ｂ）に示ように基板１の背面から紫外光１２−２を照
射して露光を施す。In this invention, as shown in FIG. 1, the photoresist layers 5-1 and 5-2 have a two-layer structure, and the thick first photoresist layer 5-1 is thinly formed as shown in FIG. The entire surface of the substrate 1 is irradiated with ultraviolet light 12-1 from the top to expose it, and is made transparent to the second ultraviolet light.After this, a thin photoresist layer 5-2 is transferred on top of the substrate 1. As shown in FIG. 2B, exposure is performed by irradiating ultraviolet light 12-2 from the back side of the substrate 1.
厚い第１のフォトレジスト層５−１は前面露光によって
透明状態とされるので、これの上に形成される薄い第２
のフォトレジスト層５−２のみが背面露光の対象となる
。従って、この背面露光しかたんは前述した従来法に比
べて大幅にたんしゅつされる。即ち、この時間短縮は従
来のフォトレジスト層厚と当該第２のフォトレジスト層
厚の比の１／ｅに比例するので、例えば第２のフォトレ
ジスト層を従来のフォトレジスト層の３分の１とすると
それの背面露光時間は従来の５％となり、露光時間が大
幅に短縮される。Since the thick first photoresist layer 5-1 is made transparent by front exposure, the thin second photoresist layer formed thereon is
Only the photoresist layer 5-2 is subject to backside exposure. Therefore, this back exposure method is significantly simpler than the conventional method described above. That is, since this time reduction is proportional to 1/e of the ratio of the thickness of the conventional photoresist layer to the thickness of the second photoresist layer, for example, the second photoresist layer is reduced to one third of the thickness of the conventional photoresist layer. In this case, the back exposure time will be 5% of the conventional one, and the exposure time will be significantly shortened.
第２図は本発明による実施例の工程図であり、第３図と
同一箇所は同符号を用いる。この発明の特徴は、レジス
ト層露光の工程にある。このレジスト層露光に付いて第
２図（ｂ）と（Ｃ）を用いて説明をする。FIG. 2 is a process diagram of an embodiment according to the present invention, and the same parts as in FIG. 3 are denoted by the same reference numerals. The feature of this invention lies in the step of exposing the resist layer. This resist layer exposure will be explained using FIGS. 2(b) and 2(C).
第２図（ｂ）の工程において、ａ−Ｓｔ：Ｈ膜よりなる
半透明動作半導体膜４の上に、第１のフォトレジストｒ
ｇ５−１を１．５ μｍ厚さに形成する。この厚いフォ
トレジスト層５−１にガラス基Ｆｉ１の上部（前面）か
ら紫外光１２−１を照射しフォトレジスト層５−１の露
光を行う、露光された第１のフォトレジスト層５−１は
、紫外光に対して透過性のものとなる。In the step of FIG. 2(b), a first photoresist r is applied on the semitransparent operating semiconductor film 4 made of a-St:H film
g5-1 is formed to a thickness of 1.5 μm. This thick photoresist layer 5-1 is irradiated with ultraviolet light 12-1 from the top (front side) of the glass base Fi1 to expose the photoresist layer 5-1.The exposed first photoresist layer 5-1 is , it becomes transparent to ultraviolet light.
次ぎに、第２図（Ｃ）の工程において、透明状態とされ
た第１のフォトレジスト層５−１上に、第２のフォトレ
ジストＩ’ｔｉ５−２を０．５ μｍ厚さに形成した後
、この薄いフォトレジスト層をガラス基板１の背面から
紫外光１２−２を照射して露光を行う。ここで、仮に従
来方法で１．５μｍ厚を有するフォトレジスト層の背面
露光に９０分の露光時間を要していた工程が、この発明
では５分で終了することとなる。Next, in the step of FIG. 2(C), a second photoresist I'ti5-2 was formed to a thickness of 0.5 μm on the first photoresist layer 5-1 which had been made transparent. Thereafter, this thin photoresist layer is exposed to ultraviolet light 12-2 from the back side of the glass substrate 1. Here, in the conventional method, a process that required 90 minutes of exposure time for back exposure of a photoresist layer having a thickness of 1.5 μm can be completed in 5 minutes in the present invention.
この背面露光を終了した後の第２図（ｄ）〜（「）の工
程は、従来の第３図（Ｃ）〜（ｅ）と同一であるので説
明を省略する。The steps shown in FIGS. 2(d) to 2(') after completing this back exposure are the same as the conventional steps shown in FIGS. 3(c) to 3(e), and therefore their explanation will be omitted.
以上の説明から明らかなように、この発明によれば、自
己整合パターン用の背面露光時間の短縮が行えるので、
自己整合型の薄膜トランジスタを製作する上できわめて
有効な効果を奏する。As is clear from the above description, according to the present invention, the back exposure time for self-aligned patterns can be shortened.
This is extremely effective in manufacturing self-aligned thin film transistors.
第１図は本発明の原理図、
第２図は本発明による実施例の工程図、第３図は従来の
自己整合型の薄膜トランジスタの製造工程図である。
図において、１はガラス基板、２は不透明ゲート電極、
３はゲート絶縁膜、４は半透明動作半導体膜、５−１は
第１のフォトレジスト層、５−２は第２のフォトレジス
ト層、１２−１と１２−２は紫不発明の原理図
第１図
／Ｉｆ１１巳による＊施イ刊のエボ）刀第２図
第３図FIG. 1 is a principle diagram of the present invention, FIG. 2 is a process diagram of an embodiment of the present invention, and FIG. 3 is a manufacturing process diagram of a conventional self-aligned thin film transistor. In the figure, 1 is a glass substrate, 2 is an opaque gate electrode,
3 is a gate insulating film, 4 is a semi-transparent operating semiconductor film, 5-1 is a first photoresist layer, 5-2 is a second photoresist layer, 12-1 and 12-2 are diagrams of the principle of Shifu invention Figure 1/Evo published by If11 Mi) Sword Figure 2 Figure 3
Claims (1)
ート絶縁膜（３）、半透明の動作半導体膜（４）を成層
して形成し、その上に前記ゲート電極（２）をマスクと
して露光法によりゲート電極に整合するフォトレジスト
層の自己整合パターン（５）を形成する薄膜トランジス
タの製造方法において、 前記自己整合パターン（５）は、半透明動作半導体膜（
４）上に厚い第１のフォトレジスト層（５−１）を形成
したる後に、該第１のフォトレジスト層（５−１）を前
記基板上部より全面露光をする工程と、露光され透光性
となった第１のフォトレジスト層（５−１）上に薄い第
２のフォトレジスト層５−２を形成した後、該第２のフ
ォトレジスト層を基板背面から露光する工程と、これら
２像のフォトレジスト層（５−１、５−２）を現像する
工程を含んで形成されることを特徴とする自己整合型薄
膜トランジスタの製造方法。[Claims] An opaque gate electrode (2), a gate insulating film (3), and a semitransparent active semiconductor film (4) are formed on the surface of a transparent substrate (1), and the gate electrode is formed on the surface of the transparent substrate (1). In a method for manufacturing a thin film transistor in which a self-aligned pattern (5) of a photoresist layer that is aligned with a gate electrode is formed by an exposure method using an electrode (2) as a mask, the self-aligned pattern (5) is formed of a semi-transparent operating semiconductor film (
4) After forming a thick first photoresist layer (5-1) on the substrate, the first photoresist layer (5-1) is exposed to light from above the substrate, and the first photoresist layer (5-1) is exposed to light and transparent. After forming a thin second photoresist layer 5-2 on the first photoresist layer (5-1) which has become transparent, a step of exposing the second photoresist layer to light from the back side of the substrate; A method for manufacturing a self-aligned thin film transistor, comprising the step of developing a photoresist layer (5-1, 5-2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61224729A JPS6379379A (en) | 1986-09-22 | 1986-09-22 | Manufacture of self-alignment type thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61224729A JPS6379379A (en) | 1986-09-22 | 1986-09-22 | Manufacture of self-alignment type thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6379379A true JPS6379379A (en) | 1988-04-09 |
Family
ID=16818327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61224729A Pending JPS6379379A (en) | 1986-09-22 | 1986-09-22 | Manufacture of self-alignment type thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6379379A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264383A (en) * | 1991-06-28 | 1993-11-23 | U.S. Philips Corp. | Method of manufacturing a thin film transistor |
| JP2009206388A (en) * | 2008-02-29 | 2009-09-10 | Toyama Univ | Thin film transistor, and manufacturing method thereof |
-
1986
- 1986-09-22 JP JP61224729A patent/JPS6379379A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264383A (en) * | 1991-06-28 | 1993-11-23 | U.S. Philips Corp. | Method of manufacturing a thin film transistor |
| JP2009206388A (en) * | 2008-02-29 | 2009-09-10 | Toyama Univ | Thin film transistor, and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6635581B2 (en) | Method for forming a thin-film transistor | |
| JPH10163174A (en) | Patterning method of thin film | |
| JPS6379379A (en) | Manufacture of self-alignment type thin film transistor | |
| JPS6239817B2 (en) | ||
| JPS6222463B2 (en) | ||
| JP2610402B2 (en) | Method of manufacturing T-shaped gate by double exposure | |
| JPS62152174A (en) | Manufacture of thin-film transistor | |
| JPH07226356A (en) | Pattern forming method using multilayer resistance | |
| JPS62245251A (en) | Resist pattern forming method | |
| JPH0697024A (en) | Formation of resist pattern | |
| JPH06118445A (en) | Production of liquid crystal display device | |
| JPH0658875B2 (en) | X-ray mask and pattern forming method using the same | |
| JPH0298147A (en) | Manufacture of semiconductor device | |
| JPS59165459A (en) | Manufacture of thin film transistor | |
| JPS6341077A (en) | Manufacture of thin-film transistor | |
| JPS60257171A (en) | Manufacture of thin-film semiconductor element | |
| JPH02106756A (en) | Fine pattern forming method | |
| JP2791757B2 (en) | Semiconductor mask and method of manufacturing the same | |
| JPH04345162A (en) | Mask and production thereof | |
| JP2519763B2 (en) | Method of manufacturing thin film transistor matrix | |
| JPS60235467A (en) | Manufacture of thin-film transistor | |
| JPH04298048A (en) | Manufacture of semiconductor device | |
| WO2004055917A2 (en) | Manufacture of thin film transistors | |
| JPS6189671A (en) | Manufacture of thin film semiconductor element | |
| JPS6266630A (en) | Manufacturing of semiconductor device |