JPS59165459A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS59165459A JPS59165459A JP3942883A JP3942883A JPS59165459A JP S59165459 A JPS59165459 A JP S59165459A JP 3942883 A JP3942883 A JP 3942883A JP 3942883 A JP3942883 A JP 3942883A JP S59165459 A JPS59165459 A JP S59165459A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- photosensitive resin
- resin layer
- transparent
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000011347 resin Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 210000004303 peritoneum Anatomy 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は例えば液晶表示器において表示画素の選択の
ために用いられる薄膜トランジスタの製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a thin film transistor used for selecting display pixels in, for example, a liquid crystal display.
く背 景〉
この種の薄膜トランジスタにおいて、ターンオン時間を
短かくする点及びドレイン電流を大きくする点から、ソ
ース電極及びドレイン電極の間隔、いわゆるチャネル長
を小さくすることが望まれている。チャネル長を小さく
するには、ゲート電極をフォトエツチングにより形成す
る際に用いるマスクと、ソース電極及びドレイン電極を
フォトエツチングにより形成する際に用いるマスクとの
相対位相を正確に一致させる必要があり、この点からチ
ャネル長を小さくするには限にかあった。Background In this type of thin film transistor, it is desired to reduce the distance between the source electrode and the drain electrode, the so-called channel length, in order to shorten the turn-on time and increase the drain current. In order to reduce the channel length, it is necessary to accurately match the relative phase of the mask used when forming the gate electrode by photoetching and the mask used when forming the source and drain electrodes by photoetching. From this point of view, there was a limit to how small the channel length could be.
このような点よシいわゆるセルフアライメントの手法を
用いることが提案されている。即ち透明基板にゲート電
極を不透明膜で形成し、このゲート電極を被ってゲート
絶縁膜を形成し、そのゲート絶縁膜上にアモルファスシ
リコン層を形成し、そのアモルファスシリコン層上にポ
ジタイプの感光性樹脂層を形成し、その感光性樹脂層に
対し、透明基板側から光を照射した後、現像してゲート
電極と対応する部分のみ感光性樹脂層を残し、その後、
その残った感光性樹脂層を含んで全体に金属層を形成し
、更に上記残った感光性樹脂層を除去することによりソ
ース電極及びドレイン電極を形成する。このようにすれ
ば、ソース電極及びドレイン電極の形成はゲート電極を
マスクとしているため、これら電極の位置合せを自動的
に、かつ正確に行うことができ、チャネル長を小さくす
ることができる。しかし、このようにして形成された薄
膜トランジスタによれば、アモルファスシリコン層が外
部に現われた状態となっているだめ、例えばこの薄膜ト
ランジスタを液晶表示器に用いると、アモルファスシリ
コン層が液晶と接するために動作が不安定になる。この
点より薄膜トランジスタの全体を二酸化膜などで被覆す
る必要があり、構造が複雑になる欠点がある。In view of this, it has been proposed to use a so-called self-alignment method. That is, a gate electrode is formed with an opaque film on a transparent substrate, a gate insulating film is formed covering the gate electrode, an amorphous silicon layer is formed on the gate insulating film, and a positive type photosensitive resin is formed on the amorphous silicon layer. After forming a layer and irradiating the photosensitive resin layer with light from the transparent substrate side, it is developed to leave the photosensitive resin layer only in the portion corresponding to the gate electrode, and then,
A metal layer is formed on the entire surface including the remaining photosensitive resin layer, and the remaining photosensitive resin layer is further removed to form a source electrode and a drain electrode. In this way, since the source electrode and the drain electrode are formed using the gate electrode as a mask, the alignment of these electrodes can be performed automatically and accurately, and the channel length can be reduced. However, with the thin film transistor formed in this way, the amorphous silicon layer is exposed to the outside, so if this thin film transistor is used in a liquid crystal display, for example, the amorphous silicon layer will be in contact with the liquid crystal, so it will not work. becomes unstable. From this point of view, it is necessary to cover the entire thin film transistor with a dioxide film or the like, which has the disadvantage of complicating the structure.
〈発明の概要〉
この発明の目的は短かいチャネル長を容易にかつ正確に
作ることができ、しかも構造が簡単な薄膜トランジスタ
の製造方法を提供することにある。<Summary of the Invention> An object of the present invention is to provide a method for manufacturing a thin film transistor that can easily and accurately produce a short channel length and has a simple structure.
この発明によれば透明絶縁基板上に、ゲート電極ではな
く、ドレイン電極及びソース電極を形成し、これらドレ
イン電極及びソース電極間にわたってアモルファスシリ
コン又は多結晶シリコンなど６半導体シリコン層を形成
し、その半導体シリコン層を被ってゲート絶縁膜を形成
し、このゲート絶縁膜上に透明電極を形成し、更にその
上にネガタイプの感光性樹脂層を形成し、その感光性樹
脂層に対して透明基板側より露光し、更に現像し、残っ
た感光性樹脂層をマスクとして透明電極をエツチングし
てゲート電極を得る。このようにしてゲート電極を得る
ための感光性樹脂層の露光を、ドレイン電極及びソース
電極をマスクとして行うため、つまりいわゆるセルフア
ライメント手法によりドレイン電極及びソース電極とゲ
ート電極との相対位置が正確に得られる。According to this invention, not a gate electrode but a drain electrode and a source electrode are formed on a transparent insulating substrate, six semiconductor silicon layers such as amorphous silicon or polycrystalline silicon are formed between these drain electrodes and source electrodes, and the semiconductor A gate insulating film is formed covering the silicon layer, a transparent electrode is formed on this gate insulating film, a negative type photosensitive resin layer is further formed on top of the gate insulating film, and a negative type photosensitive resin layer is formed from the transparent substrate side with respect to the photosensitive resin layer. After exposure and further development, the transparent electrode is etched using the remaining photosensitive resin layer as a mask to obtain a gate electrode. In this way, the exposure of the photosensitive resin layer to obtain the gate electrode is performed using the drain and source electrodes as masks, so the relative positions of the drain and source electrodes and the gate electrode are precisely determined by the so-called self-alignment method. can get.
〈実施例〉
次にこの発明による薄膜トランジスタの製造方法の実施
例を図面を参照して説明しよう。<Example> Next, an example of the method for manufacturing a thin film transistor according to the present invention will be described with reference to the drawings.
第１図に示すようにガラスなどの透明絶縁基板１１上に
、ニクロム、クロム、モリブデンなどの不透明金属層を
、１０００〜２００ＯＡ程度、蒸着あるいはスパッタリ
ングにょｐ形成し、更にフォトエツチングによりドレイ
ン電極１２及びソース電極１３を形成する。As shown in FIG. 1, on a transparent insulating substrate 11 such as glass, an opaque metal layer such as nichrome, chromium, or molybdenum is formed with a thickness of about 1000 to 200 OA by vapor deposition or sputtering, and then the drain electrode 12 and the like are formed by photoetching. A source electrode 13 is formed.
これらドレイン電極１２及びソース電極１３を含み透明
基板１１上にアモルファスシリコン、多結晶シリコンな
どの半導体シリコン層を例えば３０００Ａの厚さで、プ
ラズマＣＶＤ（化学的気相成長）法によシ形成し、これ
に対してフォトエツチングによＩ）第２図に示すように
トレイン電極１２及びソース電極１３にまたがった半導
体ンリコン層１４、いわゆるチャネル領域を形成する。A semiconductor silicon layer such as amorphous silicon or polycrystalline silicon is formed on the transparent substrate 11 including the drain electrode 12 and the source electrode 13 to a thickness of, for example, 3000 A by a plasma CVD (chemical vapor deposition) method, On the other hand, by photo-etching, I) a semiconductor silicon layer 14 extending over the train electrode 12 and the source electrode 13, a so-called channel region, is formed as shown in FIG.
次に半導体シリコン層１４の全体を被って透明基板１１
上にゲート絶縁膜１５を第３図に示すように形成する。Next, a transparent substrate 11 is placed over the entire semiconductor silicon layer 14.
A gate insulating film 15 is formed thereon as shown in FIG.
ゲート絶縁膜１５は例えば窒化シリコン（ＳｉＮ２）又
は二酸化シリコンの２０００〜３０００Ｘの層からなシ
、プラズマＣＶＤ法により形成することができる。The gate insulating film 15 is, for example, a 2000 to 3000× layer of silicon nitride (SiN2) or silicon dioxide, and can be formed by plasma CVD.
更に第４図に示すようにゲート絶縁膜１５上に１０００
久以下、例えば４００〜５００Ａ程度の厚さの透明電極
１６を、Ｉ Ｔ Ｏ（Ｉｎ２０ｇ及びＳｎ□＋の混合物
）又は酸化錫を蒸着、あるいはスパッタリングにより形
成する。透明電極１６上にネガタイプの感光性樹脂層１
７を形成する。この感光性樹脂層１７に対し、透明基板
１１側から紫外線１８を露光する。Furthermore, as shown in FIG.
A transparent electrode 16 having a thickness of, for example, about 400 to 500 A is formed by vapor deposition or sputtering of ITO (a mixture of 20 g of In and Sn□+) or tin oxide. Negative type photosensitive resin layer 1 on transparent electrode 16
form 7. This photosensitive resin layer 17 is exposed to ultraviolet light 18 from the transparent substrate 11 side.
この露光により感光性樹脂層１７の光が照射された部分
は硬化する。従って現像すると、第５図に示すように、
ドレイン電極１２及びソース電極１３が、マスクとして
作用した感光性樹脂層のパターン１７ｐが形成される。By this exposure, the portion of the photosensitive resin layer 17 that is irradiated with light is cured. Therefore, when developed, as shown in Figure 5,
A pattern 17p of the photosensitive resin layer is formed using the drain electrode 12 and the source electrode 13 as a mask.
この感光性樹脂層のパターン１７ｐをマスクとして透明
電極１６をエツチングして第６図に示すように感光性樹
脂層のパターン１７ｐで被われた部分の透明電極がゲー
ト電極１６ｇとして得られる。The transparent electrode 16 is etched using the pattern 17p of the photosensitive resin layer as a mask to obtain a portion of the transparent electrode covered by the pattern 17p of the photosensitive resin layer as a gate electrode 16g as shown in FIG.
く効 果〉
この実施例に示すように、予め形成したドレイン電極１
２、ソース電極１３をマスクとして露光現像することに
よシゲート電極１６ｇの位置が決定され、いわゆるセル
フアライメントがなされ、ドレイン電極１２及びソース
電極１３とゲート電極１６ｇとの相対位相は必ず一定の
関係となシ、ドレイン電極−１２及びソース電極１３の
間隔を小とし、いわゆるチャネル長りを小さくすること
ができ、従ってターンオン時間が短かく、かつドレイン
電流が大きいものを容易に得ることかでき、かつ、この
薄膜トランジスタを、大面積、高集積度のマトリックス
アレイとして実現し、しかもその素子間のバラツキを著
しく小さくすることが可能である。また第６図から理解
されるように半導体シリコン層１３、いわゆるチャネル
領域はゲート絶縁膜１５で被われているため、外部と接
触することがなく、例えば液晶表示器内に用いても、特
に保腹膜を形成しなくても安定に動作するものとなシ、
それぞれ構造が筒中、なものと々る。Effect> As shown in this example, the drain electrode 1 formed in advance
2. The position of the gate electrode 16g is determined by exposure and development using the source electrode 13 as a mask, and so-called self-alignment is achieved, so that the relative phases of the drain electrode 12 and the source electrode 13 and the gate electrode 16g are always in a constant relationship. Moreover, the distance between the drain electrode 12 and the source electrode 13 can be made small, so that the so-called channel length can be made small, and therefore a device with a short turn-on time and a large drain current can be easily obtained. , it is possible to realize this thin film transistor as a large-area, highly integrated matrix array, and to significantly reduce variations among the elements. Furthermore, as can be understood from FIG. 6, the semiconductor silicon layer 13, the so-called channel region, is covered with the gate insulating film 15, so it does not come into contact with the outside, and even when used in, for example, a liquid crystal display, it is particularly safe. It must operate stably even without the formation of a peritoneum.
Each of them has a different structure.
なおドレイン電極１２．は、ソース電極１３はゲート電
極１６ｇの形成時のセルフアライメントに必要表部分の
みが不透明であればよく、その他は透明でもよく、例え
ば液晶表示器に用いる場合は画素電極とする部分は透明
電極とされる。Note that the drain electrode 12. For the source electrode 13, only the surface portion required for self-alignment during formation of the gate electrode 16g needs to be opaque, and the rest may be transparent. For example, when used in a liquid crystal display, the portion to be used as a pixel electrode may be a transparent electrode. be done.
第１図乃至第６図はこの発明の一実施例の工程を説明す
るための断面図である。
１１：透明絶縁基板、１２ニドレイン電極、１３：ソー
ス電極、１４：半導体シリコン層、１５：ゲート絶縁膜
、１６：透明電極、１６ｇ：ゲート電極、１７：感光性
樹脂層、１８：紫外線。
特許出願人 星電器製造株式会社
代理人草野 卓
オ １ 図
１７２１Ｄ
４
斧４ ダ
飢１ｓ’ ＬＢＪ
オ ５図
４
ル６肥1 to 6 are cross-sectional views for explaining the steps of an embodiment of the present invention. 11: Transparent insulating substrate, 12 Ni-drain electrode, 13: Source electrode, 14: Semiconductor silicon layer, 15: Gate insulating film, 16: Transparent electrode, 16g: Gate electrode, 17: Photosensitive resin layer, 18: Ultraviolet rays. Patent Applicant Hoshi Denki Manufacturing Co., Ltd. Agent Takuo Kusano 1 Figure 1721D 4 Ax 4 Daki 1s' LBJ O 5 Figure 4 Le 6 Fa
Claims (1)
ス電極を形成する工程と、これらドレイン電極及びソー
ス電極間にわたって半導体シリコン層を上記基板上に形
成する工程と、その半導体シリコン層を被ってゲート絶
縁膜を形成する工程と、そのゲート絶縁膜上に透明電極
を形成する工程と、その透明電極上に、光により硬化す
る感光性樹脂層を形成する工程と、上記基板側から上記
ドレイン電極及びソース電極をマスクとして上記感光性
樹脂層に光を照射した後、現像して上記感光性樹脂層の
光が照射されない部分を除去する工程と、その現稼によ
υ残った感光性樹脂層をマスクとして上記透明電極をエ
ツチングしてゲート電極を作る工程とを有する薄膜トラ
ンジスタの製造方法。(1) A step of forming an opaque drain electrode and a source electrode on a transparent insulating substrate, a step of forming a semiconductor silicon layer on the substrate between the drain electrode and the source electrode, and a step of forming a semiconductor silicon layer covering the semiconductor silicon layer to form a gate. a step of forming an insulating film, a step of forming a transparent electrode on the gate insulating film, a step of forming a photosensitive resin layer that is cured by light on the transparent electrode, and a step of forming the drain electrode and the transparent electrode from the substrate side. After irradiating the photosensitive resin layer with light using the source electrode as a mask, developing the photosensitive resin layer to remove the portions of the photosensitive resin layer that are not irradiated with light; A method for manufacturing a thin film transistor, comprising the step of etching the transparent electrode as a mask to form a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3942883A JPS59165459A (en) | 1983-03-09 | 1983-03-09 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3942883A JPS59165459A (en) | 1983-03-09 | 1983-03-09 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59165459A true JPS59165459A (en) | 1984-09-18 |
Family
ID=12552723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3942883A Pending JPS59165459A (en) | 1983-03-09 | 1983-03-09 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59165459A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230376A (en) * | 1985-07-31 | 1987-02-09 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPH02203539A (en) * | 1989-02-01 | 1990-08-13 | Nec Corp | Formation of tft array |
| US6380009B1 (en) | 1999-03-27 | 2002-04-30 | U.S. Philips Corporation | Method of manufacturing thin film transistors |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5818966A (en) * | 1981-07-27 | 1983-02-03 | Toshiba Corp | Manufacture of thin film field-effect transistor |
-
1983
- 1983-03-09 JP JP3942883A patent/JPS59165459A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5818966A (en) * | 1981-07-27 | 1983-02-03 | Toshiba Corp | Manufacture of thin film field-effect transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230376A (en) * | 1985-07-31 | 1987-02-09 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPH02203539A (en) * | 1989-02-01 | 1990-08-13 | Nec Corp | Formation of tft array |
| US6380009B1 (en) | 1999-03-27 | 2002-04-30 | U.S. Philips Corporation | Method of manufacturing thin film transistors |
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