JPS6378417U - - Google Patents
Info
- Publication number
- JPS6378417U JPS6378417U JP17088886U JP17088886U JPS6378417U JP S6378417 U JPS6378417 U JP S6378417U JP 17088886 U JP17088886 U JP 17088886U JP 17088886 U JP17088886 U JP 17088886U JP S6378417 U JPS6378417 U JP S6378417U
- Authority
- JP
- Japan
- Prior art keywords
- gain
- control circuit
- input terminal
- ground
- gain control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の利得制御回路の構成図、第２
図は同利得制御回路の一実施例を示す具体回路図
、第３図は第２図に示す回路の周波数利得特性図
、第４図は従来の利得制御回路の構成図、第５図
は増幅器のオフセツト電圧の発生を示す説明図で
ある。
図中、１３は増幅器、ＩＮは入力端子、ＯＵＴ
は出力端子、Ｒ３は分圧抵抗、ｂｎはデジタル符
号信号としてのＡＧＣコントロール信号、Ｃはコ
ンデンサである。
Figure 1 is a configuration diagram of the gain control circuit of the present invention, Figure 2
The figure is a specific circuit diagram showing one embodiment of the gain control circuit, Figure 3 is a frequency gain characteristic diagram of the circuit shown in Figure 2, Figure 4 is a block diagram of a conventional gain control circuit, and Figure 5 is an amplifier. FIG. 3 is an explanatory diagram showing the generation of an offset voltage. In the figure, 13 is an amplifier, IN is an input terminal, and OUT
is an output terminal, R3 is a voltage dividing resistor, bn is an AGC control signal as a digital code signal, and C is a capacitor.
Claims (1)
その分圧値を入力端子に帰還させると共にデジタ
ル符号信号により可変して利得設定を変更する利
得制御回路において、上記入力端子に充電電圧を
帰還させて直流利得を所定値に抑圧するコンデン
サを上記分圧抵抗と接地間に介挿したことを特徴
とする利得制御回路。 Ground the output terminal of the amplifier via a voltage dividing resistor,
In a gain control circuit that feeds back the divided voltage value to the input terminal and changes the gain setting by varying it with a digital code signal, a capacitor that feeds back the charging voltage to the input terminal and suppresses the DC gain to a predetermined value is connected to the above-mentioned portion. A gain control circuit characterized by being inserted between a piezoresistor and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17088886U JPS6378417U (en) | 1986-11-08 | 1986-11-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17088886U JPS6378417U (en) | 1986-11-08 | 1986-11-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6378417U true JPS6378417U (en) | 1988-05-24 |
Family
ID=31106015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17088886U Pending JPS6378417U (en) | 1986-11-08 | 1986-11-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6378417U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022002384A (en) * | 2020-06-22 | 2022-01-06 | 横河電機株式会社 | Amplifier circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792911A (en) * | 1980-10-08 | 1982-06-09 | Philips Nv | Circuit device with electronically controllable transmission characteristic |
-
1986
- 1986-11-08 JP JP17088886U patent/JPS6378417U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792911A (en) * | 1980-10-08 | 1982-06-09 | Philips Nv | Circuit device with electronically controllable transmission characteristic |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022002384A (en) * | 2020-06-22 | 2022-01-06 | 横河電機株式会社 | Amplifier circuit |
| US11658629B2 (en) | 2020-06-22 | 2023-05-23 | Yokogawa Electric Corporation | Amplifier circuit |