JPS6378294A - Power source controller - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A power supply control device configured to detect an abnormal overcurrent in a shorter detection time than the detection time of an abnormally low voltage at the output terminal of a power supply, This prevents the processing equipment that performs processing corresponding to each overcurrent from mistaking the occurrence of an overcurrent alarm as a low voltage alarm.

[Industrial application field]

The present invention relates to a power supply control device, and more particularly to a power supply control device that effectively detects overcurrent at an output terminal of a power supply.

DC/DC converters and the like are used as power sources for computers and the like. An abnormality at the output end of the power supply is output as a low voltage alarm signal indicating an abnormal drop in output voltage or an overcurrent alarm signal indicating an abnormal overcurrent in the output current due to a short circuit in the load or the like. The processing device stores these alarm signals as maintenance information, for example, in a memory or displays them on a display device.

[Conventional technology]

FIG. 5 is a block circuit diagram showing an example of a conventional power supply control device, and FIG. 6 is a waveform diagram illustrating the operation of the device shown in FIG. 4.

As shown in FIG. 5, conventionally, the low voltage alarm output from the power supply 1 is input to one input of the AND gate 51 in the power supply control device 50, and the overcurrent alarm signal output from the power supply 1 is input to one input of the AND gate 51. The signal is input to an inverter gate 52 in the control device 50. The output of inverter gate 52 is connected to the other input of AND gate 51.

And, - The processing device 40 in the power supply control device 50 is
The output of the ND gate 51 is received as an effective low voltage alarm signal, and the output of the inverter gate 52 is received as an effective overcurrent alarm signal, and processing corresponding to each alarm signal is performed.

[Problem that the invention seeks to solve]

The power supply 1 is realized by a DC/DC converter, etc., and has an internal current transformer and rectifier circuit, so in the event of an overcurrent such as a short circuit of the output terminal of the power supply, the 6th
As shown in the figure, the low voltage alarm signal rises at the same time as the output terminal is shorted, but the overcurrent alarm signal rises with a delay. Therefore, the effective low voltage alarm signal is sent to the processing device 40 before the effective overcurrent alarm signal. Therefore, even though an overcurrent accident has actually occurred, the processing device 40 takes action to deal with the abnormal low voltage based on the valid low voltage alarm signal that is the first valid alarm signal received. , for example, turning off the power, recording in memory, displaying on a display device, etc. Based on the information recorded in the memory or the information displayed on the display device, maintenance personnel mistakenly assume that the fault is a low voltage abnormality and work to remove the fault, but it is actually an overcurrent fault. Therefore, there is a problem in that it interferes with the work of removing obstacles.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the power supply control device of the present invention.

In FIG. 1, the power supply control device includes a low voltage alarm signal detection means 2, an overcurrent alarm signal detection means 3, and a processing device 4.

The low voltage alarm signal detection means 2 outputs an effective low voltage alarm signal after detecting an abnormally low voltage at the output end of the power supply 1 for a first predetermined time t1.

The overcurrent alarm signal detection means 3 outputs an effective overcurrent alarm signal after detecting an abnormal overcurrent at the output end of the power supply 1 for a first predetermined time t and a second predetermined time t2, which is shorter.

The processing device 4 performs processing corresponding to the effective low voltage alarm signal and the effective overcurrent alarm signal, respectively.

[For production]

Since the abnormal overcurrent detection time is shorter than the abnormal low voltage detection time, even if the overcurrent alarm signal is output from the power supply later than the low voltage alarm signal, the effective overcurrent alarm signal will be output before the effective low voltage alarm signal. Sent to a processing device. Therefore, the processing device 4 can reliably recognize that a fault due to overcurrent has occurred.

〔Example〕

FIG. 2 is a circuit diagram illustrating an embodiment of the present invention.

In FIG. 2, the low voltage alarm signal detecting means 2 connects an AND gate 21 through which a low voltage alarm signal from a power source 1 passes according to a clock signal from a clock generator 6, and an output of the AND gate 21 to detect a low voltage. When the alarm signal is at a high level "H", the first predetermined time 1+ (for example, 1
00 clock pulses), the output is set to high level "H", the low level of the low voltage alarm signal is used as the clear signal CLR to clear the count value, and the output is set to low level. counter 22 that drops the low voltage alarm signal from voltage #1 to counter 2.
and an AND gate 23 that passes the output according to the output of 2.

The overcurrent alarm signal detection means 3 includes an AND gate 31 that allows the overcurrent alarm signal from the power supply 1 to pass according to a clock signal from the clock generator 6;
1 for a first predetermined period of time when the overcurrent alarm signal is at a high level "H". a shorter second predetermined time t
While counting z (for example, 5 clock pulses), the output is set to high level 5H'', and after the above count, the overcurrent alarm signal is used as the clear signal CLR to clear the count value, and the output is set to low level "L". The counter 32 includes a counter 32 that outputs a signal from the power source 1, and an AND gate 33 that allows an overcurrent alarm signal from the power source 1 to pass depending on the output of the counter 32.

As is clear from the waveform explanatory diagram of FIG. 3, the operation of the circuit shown in FIG. 2 is as follows: overcurrent alarm detection time t2 is set to low voltage alarm detection time 1. (so that even if the overcurrent alarm signal is sent out from current 1 a time d later than the low voltage alarm signal, the effective overcurrent alarm signal is sent to the processing device before the effective low voltage alarm signal. Therefore, the processing device 4 does not mistakenly recognize that the fault in the power supply I is a low voltage even though it is an overcurrent.

When the alarm information becomes low level "L" during alarm signal detection, the counters 22 and 32 each become a clear signal CLR and the contents are reset. Therefore, even if an alarm signal is instantaneously generated due to noise or the like, there is an advantage that it is not transmitted to the processing device.

In FIG. 2, a power supply control device using a counter and an A N D gate is shown as an example, but the power supply control device according to the present invention may be constructed using a microprocessor, in which case the counter The counting time can be set in read-only memory (ROM).

FIG. 3 is a block diagram showing an example of a power control device using a microprocessor according to another embodiment of the present invention.

In Figure 3, power supply unit 1-1.1-2゜1-3
is turned on by the power-on signal (PONI, 2, 3) from the power-on signal register (FF) 10,
Power is supplied to the load 11. Power supply unit 1-1.1-
When a low voltage alarm signal (Under Voltage Alarm IJVAI, 2.3) is generated from any of 2.1-3, this alarm signal is sent to the receiver (RV) 12 - data bus D0-D, - bidirectional bus sofa ( TRV) 13
The data is input to the microprocessor (MPU) 14 via the microprocessor (MPU) 14. Similarly, an overcurrent alarm signal (overcurrent alarm signal) from any of the power supply units 1-1.1-2.1-3.
Alarm DCA I.

2.3), this alarm signal is sent to the receiver (
RV) 15 - data bus Do xDt - bidirectional huffer (TRV)
U) Input to 14. The microprocessor 14 receives an address bus A0 depending on whether the received alarm signal is a low voltage alarm signal UVA or an overcurrent alarm signal OCA.
~A l through 15? Access the corresponding address of o1116 and check the detection time 1. Or read t2. After counting the detection time on the program, a control signal is sent to the timing circuit 17, and the address of the power supply unit in which the fault has occurred and the details of the fault are stored in a predetermined area of the RAM 18. Timing circuit 17 is connected to address bus A0
- Controls the timing of writing (WT) to RAM 17 and reading (RD) from RAM 17 according to the address signal from AIS and the above control signal, and sets the power-on signal register 10 to prevent failures from occurring. Turn off the power-on signal PON of the power supply unit. Further, the write timing signal (WT) from the timing circuit 19 is also set to the flip-flop 19,
A service processor (not shown) is used as an alarm signal.
VP). flip flop 10 and 1
9 is reset by a reset signal sent from the microprocessor 14 via data buses D0 to D when the alarm signal from the power supply unit disappears.

RA? The alarm information stored in + 18 is displayed on a display device (not shown) or output from a printer (not shown), and is used as fault information for maintenance personnel.

In the embodiment shown in FIG. 4 as well, by significantly shortening the detection time t2 stored in the ROM 16 by t, the second
The same effects as the embodiment shown in the figure can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, by making the detection time of the overcurrent alarm signal of the power supply significantly shorter than the detection time of the low voltage alarm signal, an overcurrent failure occurs in the power supply control device. It is possible to prevent faults from being mistaken for low voltage faults even though the fault is low, allowing maintenance personnel to perform fault recovery work more efficiently.

Furthermore, since the alarm signal is determined as a valid alarm signal after being detected for a predetermined amount of time, misidentification of the alarm signal due to noise or the like can be prevented.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit diagram explaining one embodiment of the present invention, Fig. 3 is a waveform explanatory diagram of the circuit of Fig. 2, and Fig. 4 is a diagram illustrating another embodiment of the present invention. FIG. 5 is a block diagram illustrating an embodiment, FIG. 5 is a circuit diagram illustrating a conventional power supply control device, and FIG. 6 is a waveform diagram illustrating problems with the conventional power supply control device. 1...Power supply,

Claims (1)

[Scope of Claims] Low voltage alarm signal detection means (2) for outputting a valid low voltage alarm signal after detecting abnormal low voltage at the output end of the power supply (1) for a first predetermined time (t_1); overcurrent alarm signal detection for outputting a valid overcurrent alarm signal after detecting an abnormal overcurrent at the output terminal of the voltage (2) for a second predetermined time (t_2) shorter than the first predetermined time (t_1); A power supply control device comprising means (3) and a processing device (4) that performs processing corresponding to the effective low voltage alarm signal and the effective overvoltage alarm signal, respectively.