JPS6377184A - Manufacture of semiconductor laser array - Google Patents

Manufacture of semiconductor laser array

Info

Publication number
JPS6377184A
JPS6377184A JP22258986A JP22258986A JPS6377184A JP S6377184 A JPS6377184 A JP S6377184A JP 22258986 A JP22258986 A JP 22258986A JP 22258986 A JP22258986 A JP 22258986A JP S6377184 A JPS6377184 A JP S6377184A
Authority
JP
Japan
Prior art keywords
layer
current confinement
thickness
substrate
grooves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22258986A
Other languages
Japanese (ja)
Inventor
Kenji Kawashima
川島 健児
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP22258986A priority Critical patent/JPS6377184A/en
Publication of JPS6377184A publication Critical patent/JPS6377184A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/40Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/4025Array arrangements, e.g. constituted by discrete laser diodes or laser bar
    • H01S5/4031Edge-emitting structures

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To effectively manufacture a semiconductor laser array in such a manner that laser lights generated in an active layer are individually separated by absorbing light generated in the active layer directly on a current constriction layer by a thin first clad layer of the part to the current constriction layer. CONSTITUTION:A current constriction layer 13 which has a predetermined thickness and a flat surface is laminated directly on a stripe 12 on a substrate 11. Then, a plurality of grooves 14 extended perpendicular to this paper are formed on the whole layer 13. Such grooves 14 are formed at a depth larger than the thickness of the layer 13 directly above the mesa stripe 12 and smaller than the thickness of the layer 13 on the substrate 11 except the stripe 12, and so etched that the interval is set to a predetermined value and the widths of the layer 13 perpendicular to the extending direction of the groove are all of a predetermined value. Thereafter, a first clad layer 15 made of P-type Ga0.55Al0.45As and a second clad layer 17 made of nondoped Ga0.85Al0.15As are sequentially laminated by a liquid growing method on the layer 13 to form an oscillator layer 18, and a cap layer 19 made of n-type GaAs is thereafter grown on the layer 17.

Description

【発明の詳細な説明】 ビ) 産業上の利用分野 本発明は半導体レーザアレイの製造方法に関する。[Detailed description of the invention] B) Industrial application field The present invention relates to a method for manufacturing a semiconductor laser array.

−1従来の技術 第2図+!Lト101は従来のvsxs型レーザを基本
とした半導体レーザアレイの製造方法を示す工程別断面
図である。
-1 Conventional technology Figure 2+! FIG. 101 is a cross-sectional view of each step showing a method of manufacturing a semiconductor laser array based on a conventional vsxs type laser.

斯る方法ではまずp型GaA3基板(1)上にn型Ga
Alからなる電流狭窄1!# (21を形成する(第2
図(a))。次いで、電流狭窄層(2)表面より基板(
1)に達する深さを有し、かつ紙面垂直方向に延在する
溝(3)を基板(1)上に配列されるべき半導体レーザ
の個数分1等間隔で形成するC′?J112図(bl)
In this method, first, n-type Ga is deposited on a p-type GaA3 substrate (1).
Current confinement 1 made of Al! # (forming 21 (second
Figure (a)). Next, the substrate (
1), grooves (3) extending perpendicular to the plane of the paper are formed at regular intervals equal to the number of semiconductor lasers to be arranged on the substrate (1). J112 figure (bl)
.

その後、電流狭窄l11123表面にp型C)&1−X
Al x A a (0<x<1)からなるMlり?7
ド、h(4)、 / yドーグ()al−4AA’YA
l(0≦Yく0、Y<X)からなる活性111T51.
 n型()lLl −XAlxAmからなる第2クラッ
ド層(6)及びn型G&AIIからなるキャップ層(7
)を順次積層する(!g2図(C))。
After that, the current confinement l11123 surface has p-type C)&1-X
Ml consisting of Al x A a (0<x<1)? 7
Do, h (4), / y Dog () al-4AA'YA
Activity 111T51.l (0≦Y×0, Y<X).
A second cladding layer (6) made of n-type ()lLl-XAlxAm and a cap layer (7) made of n-type G&AII.
) are sequentially stacked (!g2 (C)).

このようにして形成された半導体レーデアレイは理論的
i:は基板(1)とキャップ@(7)との間に順方向バ
イアスを印加すると溝(3)直上以外の活性層(5)よ
り生じた光はバンドギャップエネルギが小なる電流狭窄
層(41C吸収されるため、溝(3)直上の活性II 
!51内で生じた光のみが各溝単位で分離されたレーザ
光として出力されることとなる。
The semiconductor radar array formed in this way has a theoretical i: when a forward bias is applied between the substrate (1) and the cap@(7), it is generated from the active layer (5) other than directly above the groove (3). Since the light is absorbed by the current confinement layer (41C) with a small bandgap energy, the active II layer directly above the groove (3)
! Only the light generated within the groove 51 is output as a laser beam separated by each groove.

然るC二、半導体レーザアレイの場合、レーザ間の距離
をできる限り小さくする(1μm程度)必要があり、こ
のため溝(3)間の電流狭窄層(2)の幅は第2因(t
llより明らかな如く溝(3)が形成されていない頭載
の電流狭窄層(2)の幅より非常に狭くなる。
However, in the case of a semiconductor laser array, it is necessary to make the distance between the lasers as small as possible (approximately 1 μm), and for this reason, the width of the current confinement layer (2) between the grooves (3) is determined by the second factor (t).
As is clear from ll, the width is much narrower than the width of the overhead current confinement layer (2) in which the groove (3) is not formed.

従って!J1クラッド層(4)を液相成長法を用いて形
成すると第2図(elc示す如く溝(3)間の電流狭窄
層(2)のみが大きくメルトバックされその厚みが薄く
なる。このようにfi(31間の電流狭窄1(2)が薄
くなると1表面が平担なS11ククツドa (4)′I
t形成した場合この部分の第1クウツド詣(4)が予定
以上に厚くなり、斯る部分での光吸収効果が派少し、各
溝の直上の活性層(5)から出力されるレーザ光の分離
ができなくなる。
Therefore! When the J1 cladding layer (4) is formed using the liquid phase growth method, only the current confinement layer (2) between the grooves (3) is largely melted back and its thickness becomes thinner, as shown in FIG. When the current confinement 1 (2) between fi (31) becomes thinner, the surface of S11 becomes flat (4)'I
If T is formed, the first cloud (4) in this part will become thicker than expected, and the light absorption effect in this part will be enhanced, causing the laser light output from the active layer (5) directly above each groove to decrease. Separation becomes impossible.

この点に鑑みて、シャープ技報′1J133号1985
年p15〜″p13では電流狭窄層としてメルトバック
されに〈いGILAjAaを用いることが提案されてい
る。
In view of this point, Sharp Technical Report '1J133 No. 1985
From p15 to p13 in 2013, it was proposed to use GILAjAa which is melted back as a current confinement layer.

し鵠 発明が解決しようとする問題点 然る1:、電流狭窄層としてGaA/Aa’li使用す
ると溝形成時に電流狭窄層表面にIt酸化膜が発生し、
第1クラツド尚等の成長が困難となるという問題がある
Problem to be solved by the invention No. 1: When GaA/Aa'li is used as a current confinement layer, an It oxide film is generated on the surface of the current confinement layer during trench formation.
There is a problem in that it becomes difficult to grow the first crud.

に)1 問題点を解決するための手段 本発明は上記諸問題に鑑みてなされたもので。B) 1. Means to solve the problem The present invention has been made in view of the above problems.

その構成的特徴は半導体基板の表面基:メナストライプ
を形成する第1工程、上記基板表面畜二表面が平担とな
る実質的(:高抵抗の電流狭窄層を形成する′1JJ2
工程、上記メナストライブ上の電流狭窄層の層厚より大
でかつ上記メサストライプ上以外の部分ζ;形成された
電流狭窄層の層厚より小なる深さを有し、上記メサスト
ライプと平行に等間隔で延在する複数の溝を上記電流狭
窄層表面に形成する第3工程、上記溝が形成された電流
狭窄層表面に活性層と該活性層を挾装してなる一対のク
ラッド層からなる発振層を積層する第4工程からなるこ
とにある。
Its structural features include the first step of forming mena stripes on the surface of the semiconductor substrate;
step, a portion ζ larger than the layer thickness of the current confinement layer on the menastrive and other than on the mesa stripe; having a depth smaller than the layer thickness of the formed current confinement layer and parallel to the mesa stripe; A third step of forming a plurality of grooves extending at equal intervals on the surface of the current confinement layer, an active layer and a pair of cladding layers sandwiching the active layer on the surface of the current confinement layer in which the grooves are formed; The method consists of a fourth step of laminating oscillation layers.

ネ)作 用 このような方法で稼電流狭窄鳩の幅が均等であるため電
流狭窄層のメルトバックは均等に生じる。
(e) Effect: With this method, the width of the active current confinement layer is uniform, so the meltback of the current confinement layer occurs uniformly.

(へ)実施例 第1図(&l〜((11は本発明の実施例を示す。(f) Example FIG. 1 (&l~((11 shows an embodiment of the present invention.

まず、第1図(&口;示す如く製造せんとする複数の半
導体レーザが形成されるべきp型G&Aa基板CL11
表面を除いて斯る基板住り表面をエツチングし。
First, as shown in FIG.
Etch the surface of the substrate except for the surface.

紙面垂直方向ζ;延圧するメサスト911部α2を形成
する。
Direction ζ perpendicular to the plane of the paper: Mesast 911 portion α2 to be rolled is formed.

次いで第1etb口;示す如く基板(11)表面上(ニ
スドライブ部(13直上での1厚が約1μmでかつ表面
が平担となる電流狭窄Jilu3を積層する。尚、斯る
電流狭窄層αlはn型C)ILA@からなり、その成長
には液相成長法、気相成長法等周知のエピタキシャル成
長法を用いることができる。
Next, as shown in the first etb port, on the surface of the substrate (11) (varnish drive portion (13), a current confinement layer 3 having a thickness of approximately 1 μm and a flat surface is laminated. is made of n-type C) ILA@, and a well-known epitaxial growth method such as a liquid phase growth method or a vapor phase growth method can be used for its growth.

その後、vIt図10)C示す如く、電流狭窄層表面表
市に紙面垂直方向に延圧する複数の溝α4を全面に形成
する。斯る溝Iはその深さが基板のメサストライプ部+
12直上の電流狭窄層00層厚より大でか1、に溝の延
在方向と直交する方向の電流狭窄層の幅が全て242m
となるように周知のエツチング技術(こより形成される
Thereafter, as shown in FIG. 10)C, a plurality of grooves α4 are formed on the surface of the current confinement layer in a direction perpendicular to the plane of the paper. The depth of such groove I is equal to the mesa stripe portion of the substrate +
The width of the current confinement layer in the direction orthogonal to the extending direction of the groove is 242 m in all cases.
It is formed by a well-known etching technique so that

然る後、第1図を飼に示す如く上記電丸狭窄層u3上は
p型G&0.55AJ0.45Asからなる第1グプツ
ドIt&tlS、ノンドープGa O,85AJ O,
15ASからなる活性n(Lti及びn型Oa Q、5
5Al 145Aaからなる第2クラツドl1t17)
を1G次液相成長法);より積層し発mli!Q&を形
成すると共にその後第2クラツ、ドItiαη上inn
型G!LAllからなるキャップ層α9を成長させる。
After that, as shown in FIG. 1, on the electrical constriction layer u3, a first semiconductor layer consisting of p-type G&0.55AJ0.45As, non-doped GaO, 85AJO,
Active n(Lti and n-type Oa Q, 5
2nd cladding made of 5Al 145Aa l1t17)
(1G liquid phase growth method); Forming Q& and then inn on the second club, Do Itiαη
Type G! A cap layer α9 made of LAll is grown.

尚、上記第1クラッド層(1シは電流狭窄層住3上での
層厚が約0.1μmでかつその表面が平担となるように
形成されている。また活性層αQ、第2グクツド層(1
7)及びキャップIIIα9は夫々その層厚が0.05
μm、1μm及び2μm程度でかつ表面が平担となるよ
う1:形成される。
The first cladding layer (1) has a thickness of about 0.1 μm on the current confinement layer 3 and is formed so that its surface is flat. Layer (1
7) and Cap IIIα9 each have a layer thickness of 0.05
1: Formed so that the diameter is about 1 μm, 1 μm, and 2 μm, and the surface is flat.

このよう(ニジて形成された半導体レーザアレイでは、
電流狭窄mt13の幅が1μmと均一であるため、第1
クラツドbus形成時に生じる電流狭窄層α3のメルト
バックは均−C;生じる。この結果第1クラツドens
を表面平担に形成した際でも電流狭窄層a3上の第1ク
ラッド層α9は均一【二α1μm厚に制御できる。
In a semiconductor laser array formed in this way,
Since the width of the current confinement mt13 is uniform at 1 μm, the first
The meltback of the current confinement layer α3 that occurs during the formation of the cladding bus occurs uniformly. As a result, the first Clad ens
Even when formed with a flat surface, the first cladding layer α9 on the current confinement layer a3 can be controlled to have a uniform thickness of 1 μm.

従って、基板αυとキャップ層α1との間C二項方向バ
イアスを印加すると電流狭窄m(13の存HCよりスト
ライプ部112上の溝a4直上の活性m(1e及びその
周囲の活性層化において発光が生じるが、このとき電流
狭窄層(131i1[上の活性層ae内において生じた
光はその部分の第1クラッド層(15)は0.1μmと
薄いため上記光は電流狭窄II(13に吸収される。ゆ
えにストライプ部az上の溝室上の活性層αe内で生じ
たレーザ光は個々C二分離した形で取り出せる。
Therefore, when a bias in the C binomial direction is applied between the substrate αυ and the cap layer α1, light is emitted in the active layer immediately above the groove a4 on the stripe portion 112 due to the current confinement m (13). However, at this time, the light generated in the active layer ae above the current confinement layer (131i1) is absorbed by the current confinement II (13) because the first cladding layer (15) in that part is as thin as 0.1 μm. Therefore, the laser light generated within the active layer αe above the groove chamber on the stripe portion az can be extracted in the form of two separate parts.

(ト)発明の効果 本発明によれば、電流狭窄層をメルトバックされ易い材
料で形成した際でも、各レーザ光の分離を確実に行なえ
る。
(G) Effects of the Invention According to the present invention, even when the current confinement layer is formed of a material that is easily melted back, each laser beam can be reliably separated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al〜(alは本発明の実施例を示す工程別断
面図、第2図jal〜(C1は従来例を示す工程別断面
図である。 aυ・−n型GaAa基板、(121・・・メサストラ
イプ部。 (13−・・電流狭窄11.C41・・・溝、fi9・
・・第1クラッド層。 αG・・・活性層、 (17)・・・第2ククツド層、
αか・・発振層。
FIG. 1(al~(al is a cross-sectional view by process showing an embodiment of the present invention, FIG. 2jal~(C1 is a cross-sectional view by process showing a conventional example. ...Mesa stripe part. (13-...Current confinement 11.C41...Groove, fi9...
...First cladding layer. αG...Active layer, (17)...Second closed layer,
α... oscillation layer.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板の表面にメサストライプを形成する第
1工程、上記基板表面に表面が平担となる実質的に高抵
抗の電流狭窄層を形成する第2工程、上記メサストライ
プ上の電流狭窄層の層厚より大でかつ上記メサストライ
プ上以外の部分に形成された電流狭窄層の層厚より小な
る深さを有し、上記メサストライプと平行に等間隔で延
在する複数の溝を上記電流狭窄層表面に形成する第3工
程、上記溝が形成された電流狭窄層表面に活性層と該活
性層を挾装してなる一対のクラッド層からなる発振層を
積層する第4工程からなることを特徴とする半導体レー
ザアレイの製造方法。
(1) A first step of forming a mesa stripe on the surface of a semiconductor substrate, a second step of forming a substantially high-resistance current confinement layer with a flat surface on the surface of the substrate, and current confinement on the mesa stripe. a plurality of grooves having a depth greater than the layer thickness of the current confinement layer and smaller than the layer thickness of the current confinement layer formed in a portion other than the mesa stripe, and extending parallel to the mesa stripe at equal intervals; A third step of forming on the surface of the current confinement layer, and a fourth step of laminating an oscillation layer consisting of an active layer and a pair of cladding layers sandwiching the active layer on the surface of the current confinement layer where the grooves are formed. A method of manufacturing a semiconductor laser array, characterized in that:
JP22258986A 1986-09-19 1986-09-19 Manufacture of semiconductor laser array Pending JPS6377184A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22258986A JPS6377184A (en) 1986-09-19 1986-09-19 Manufacture of semiconductor laser array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22258986A JPS6377184A (en) 1986-09-19 1986-09-19 Manufacture of semiconductor laser array

Publications (1)

Publication Number Publication Date
JPS6377184A true JPS6377184A (en) 1988-04-07

Family

ID=16784838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22258986A Pending JPS6377184A (en) 1986-09-19 1986-09-19 Manufacture of semiconductor laser array

Country Status (1)

Country Link
JP (1) JPS6377184A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62115795A (en) * 1985-11-14 1987-05-27 Matsushita Electric Ind Co Ltd Semiconductor laser array device
JPS62296576A (en) * 1986-06-17 1987-12-23 Matsushita Electric Ind Co Ltd Semiconductor laser array device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62115795A (en) * 1985-11-14 1987-05-27 Matsushita Electric Ind Co Ltd Semiconductor laser array device
JPS62296576A (en) * 1986-06-17 1987-12-23 Matsushita Electric Ind Co Ltd Semiconductor laser array device

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