JPH02101784A - Manufacture of quantum well fine wire and quantum well box and quantum well fine wire laser - Google Patents

Manufacture of quantum well fine wire and quantum well box and quantum well fine wire laser

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Publication number
JPH02101784A
JPH02101784A JP25511988A JP25511988A JPH02101784A JP H02101784 A JPH02101784 A JP H02101784A JP 25511988 A JP25511988 A JP 25511988A JP 25511988 A JP25511988 A JP 25511988A JP H02101784 A JPH02101784 A JP H02101784A
Authority
JP
Japan
Prior art keywords
semiconductor
quantum well
plane
layer
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25511988A
Other languages
Japanese (ja)
Inventor
Katsuhiko Muto
勝彦 武藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP25511988A priority Critical patent/JPH02101784A/en
Publication of JPH02101784A publication Critical patent/JPH02101784A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a quantum well fine wire and a quantum well box with excellent controllability by a method wherein a step-difference is formed by etching corpuscular beam having directivity, a second semiconductor layer wherein lattice unconformity between a first semiconductor and the second semiconductor is made larger than or equal to a specified value is grown on the step-difference part, and the first semiconductor layer is grown on a substrate. CONSTITUTION:The lattice unconformity 1 between a first and a second semiconductors ¦(lattice constant of the first semiconductor)-(lattice constant of the second semiconductor)¦/(lattice constant of the first semiconductor) is made 10<-2> or more. By utilizing the GaAs substrate face orientation dependency on the growth speed of GaAs and InAs, an InAs layer 11 is selectively grown only on a step-difference part on a GaAs substrate 4 of (111) face wherein the step-difference having (100) face is formed, by corpuscular beam epitaxy. In the similar manner to the InAs growth, a GaAs layer 13 is grown on the GaAs substrate 4 by corpuscular epitaxy. Hence, the GaAs layer 13 is grown with almost the same growth speed on the whole surface of the GaAs substrate, and is grown on also the InAs layer 11 with almost the same growth speed as the growth speed. Thereby, the InAs layer 11 can be filled with the GaAs layer 13, and a quantum well fine wire 2 composed of the layer 11 can be formed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置に利用される量子井戸細線の製造
方法と量子井戸箱の製造方法および量子井戸細線を発光
領域とする量子井戸細線レーザに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a quantum well wire used in a semiconductor device, a method for manufacturing a quantum well box, and a quantum well wire laser using the quantum well wire as a light emitting region. It is.

従来の技術 近年、半導体レーザのしきい値電流の減少、温度特性の
向上、スペクトルライン幅の減少あるいはFET素子の
高速化など半導体装置の特性および機能の向上に対する
要請から、半導体基板上に異なるエネルギーギャップを
有する超薄膜を交互に積層した量子井戸構造(2次元電
子系)を用いた半導体装置の開発が、各方面で盛んに行
なわれている。第5図(−)は量子井戸構造の概念図、
第5図(b)はその状態密度を示す特性図である。量子
井戸構造1はポテンシャル障壁100と量子井戸110
からなる。第5図0は量子井戸細線の概念図、第5図中
)はその状態密度を示す特性図、また第7図(a)は量
子井戸箱の概念図、第7図(b)はその状態密度を示す
特性図である。量子井戸構造1から量子井戸細線2.量
子井戸箱3の順に電子の自由度が減少し、状態密度が尖
鋭化してくる。そのため量子井戸構造1の特性1機能を
さらに向上させる量子井戸細線2(1次元電子系)およ
び量子井戸箱3(O次元電子系)が注目されてきて、こ
れらを用いた半導体レーザ等が提案されている(固体物
理22(1987年)第71頁から第82頁)。
Background of the Invention In recent years, there has been a demand for improved characteristics and functions of semiconductor devices, such as a reduction in the threshold current of semiconductor lasers, an improvement in temperature characteristics, a reduction in spectral line width, and an increase in the speed of FET devices. 2. Description of the Related Art Semiconductor devices using a quantum well structure (two-dimensional electronic system) in which ultra-thin films having gaps are alternately stacked are being actively developed in various fields. Figure 5 (-) is a conceptual diagram of the quantum well structure.
FIG. 5(b) is a characteristic diagram showing the density of states. Quantum well structure 1 includes potential barrier 100 and quantum well 110
Consisting of Figure 50 is a conceptual diagram of a quantum well thin wire, Figure 5) is a characteristic diagram showing its density of states, Figure 7 (a) is a conceptual diagram of a quantum well box, and Figure 7 (b) is its state. It is a characteristic diagram showing density. Quantum well structure 1 to quantum well thin wire 2. The degree of freedom of electrons decreases in the order of the quantum well box 3, and the density of states becomes sharper. Therefore, the quantum well thin wire 2 (one-dimensional electronic system) and the quantum well box 3 (O-dimensional electronic system), which further improve the characteristic 1 function of the quantum well structure 1, have been attracting attention, and semiconductor lasers etc. using these have been proposed. (Solid State Physics 22 (1987), pp. 71-82).

現在、量子井戸細線2および量子井戸箱3の製造方法は
確立されていないが、以下の方法が用いられている。第
8図は、従来の量子井戸細線2の製造方法を示す工程図
である。第8図(、)に示すように、G a A s基
板4上に量子井戸層となるInAs層5とこのInAs
層5よシエネルギーギャップの大きいポテンシャル障壁
層となるG a A s層6からなる積層構造を形成す
る。次にエツチングによシ第8図(b)に示すように溝
7を形成する。このときdlの最小寸法は、リングラフ
ィの最小寸法あるいは直接描画である集束イオンビーム
のビーム径で決まる。この最小寸法は約0.1μmであ
る。さらに約0.1μmより小さなdl を得るために
は、ウェットエツチングにおけるサイドエツチングを利
用する方法がある。第8図(C)に示すように、溝7を
G a A B層eで埋め込み加工により、量子井戸様
な積層構造であり、これをエツチングによシ第9図(b
)に示すように溝7を形成する。このときのd2.d3
の最小寸法は、第8図(b)におけるdlの最小寸法と
同様に決定され、その最小寸法は約0.1μmである。
Currently, a method for manufacturing the quantum well thin wire 2 and the quantum well box 3 has not been established, but the following method is used. FIG. 8 is a process diagram showing a conventional method for manufacturing the quantum well thin wire 2. As shown in FIG. As shown in FIG. 8(,), an InAs layer 5 serving as a quantum well layer is formed on a GaAs substrate 4
A laminated structure including a GaAs layer 6 serving as a potential barrier layer having a larger energy gap than layer 5 is formed. Next, grooves 7 are formed by etching as shown in FIG. 8(b). At this time, the minimum dimension of dl is determined by the minimum dimension of phosphorography or the beam diameter of a focused ion beam for direct writing. This minimum dimension is approximately 0.1 μm. Furthermore, in order to obtain a dl smaller than about 0.1 μm, there is a method of utilizing side etching in wet etching. As shown in FIG. 8(C), the groove 7 is filled with the G a A B layer e to form a quantum well-like laminated structure, and this is etched to form a stacked structure as shown in FIG. 9(b).
) A groove 7 is formed as shown in FIG. d2 at this time. d3
The minimum dimension of is determined in the same manner as the minimum dimension of dl in FIG. 8(b), and the minimum dimension is approximately 0.1 μm.

次に第9図(C)に示すように、第8図(C)と同様な
埋め込み加工によシ量子井戸箱3が得られる。
Next, as shown in FIG. 9(C), a quantum well box 3 is obtained by the same embedding process as in FIG. 8(C).

発明が解決しようとする課題 しかし、従来の量子井戸細線2および量子井戸箱3の製
造方法において、基板上水平方向の最小寸法りがリング
ラフィの最小寸法あるいは直接描画である集束イオンビ
ームのビーム径で決tb、D値は約0.1μmである。
Problems to be Solved by the Invention However, in the conventional manufacturing method of the quantum well thin wire 2 and the quantum well box 3, the minimum horizontal dimension on the substrate is the minimum dimension of phosphorography or the beam diameter of the focused ion beam for direct writing. The determined tb, D value is approximately 0.1 μm.

量子井戸細線2および量子井戸箱3の特性および機能は
、D値が小さい(数100八以下)はど向上するため限
界があった。また約0.1μmよυ小さい値を得るには
、ウェットエツチングにおけるサイドエツチングを利用
する方法があるが、エツチング液の入シ具合いによって
エツチングむらが生じたシ、1000八層以下の安定し
たエツチング速度を持つエツチング液が得られにくいと
いった寸法制御性の悪い方法であった。
The characteristics and functions of the quantum well thin wire 2 and the quantum well box 3 have a limit because they can only be improved if the D value is small (several 1008 or less). In addition, to obtain a value as small as about 0.1 μm, there is a method of using side etching in wet etching, but if uneven etching occurs depending on the amount of etching solution applied, stable etching speeds of 1000 or less 8 layers are not possible. This method had poor dimensional control, as it was difficult to obtain an etching solution with a

本発明は、上述の問題点を鑑みて成されたもので、現行
の最小寸法である約0.1μmより小さい寸法からなる
量子井戸細線2および量子井戸箱3を制御性良く製造で
きる方法を提出することを目的とする。
The present invention has been made in view of the above-mentioned problems, and proposes a method for manufacturing quantum well wires 2 and quantum well boxes 3 having dimensions smaller than the current minimum dimension of about 0.1 μm with good controllability. The purpose is to

また、量子井戸細線2(1次元電子系)を利用した半導
体レーザについて、具体的かつ製造の容易な量子井戸細
線レーザの提案がなかった。もう一つの本発明は、具体
的かつ製造の容易な量子井戸細線を活性層とする量子井
戸細線レーザを提供することを目的とする。
Furthermore, regarding the semiconductor laser using the quantum well wire 2 (one-dimensional electronic system), there has been no proposal for a quantum well wire laser that is specific and easy to manufacture. Another object of the present invention is to provide a quantum well wire laser that uses a quantum well wire as an active layer, which is specific and easy to manufacture.

課題を解決する丸めの手段 本発明は、上述の問題点を解決するため、量子井戸細線
の製造に対して、表面が(111)面あるいは前記(1
11)面と等価な面である第1の半導体よりなる基板上
に(100)面あるいは前記(100)面と等価な面か
らなる段差を方向性をもつ粒子線によるエツチングで形
成する工程と、前記基板の前記段差部に前記第1の半導
体と第2の半導体との格子不整合1(第1の半導体の格
子定数)−(第2の半導体の格子定数)|/(第1の半
導体の格子定数)が10−2以上である前記第2の半導
体層を成長させる工程と、前記基板上に前記第1の半導
体の層を成長させる工程を備えたものである。
Means for Rounding to Solve the Problems In order to solve the above-mentioned problems, the present invention aims to solve the above-mentioned problems by providing a method for manufacturing quantum well thin wires having a (111) surface or the (111) surface.
11) forming a step formed by a (100) plane or a plane equivalent to the (100) plane on a substrate made of a first semiconductor which is a plane equivalent to the (100) plane by etching with a directional particle beam; A lattice mismatch 1 (lattice constant of the first semiconductor) - (lattice constant of the second semiconductor) |/(lattice constant of the first semiconductor) between the first semiconductor and the second semiconductor is formed in the stepped portion of the substrate. The method comprises the steps of growing the second semiconductor layer having a lattice constant (lattice constant) of 10@-2 or more, and growing the first semiconductor layer on the substrate.

また量子井戸箱の製造に対して、表面が(111)面あ
るいは前記(111)面と等価な面である第1の半導体
よりなる基板上に(100)面あるいは前記(100)
面と等価な面および非(1QO)面からなる段差を方向
性を持つ粒子線によるエツチングで形成する工程と、前
記基板の前記段差部に前記第1の半導体と第2の半導体
との格子不整合1(第1の半導体の格子定数)−(第2
の半導体の格子定数)|/(第1の半導体の格子定数)
か10 以上である前記第2の半導体の層を成長させる
工程と、前記基板上に前記第1の半導体の層を成長させ
る工程を備えたものである。
In addition, for manufacturing a quantum well box, a substrate made of a first semiconductor whose surface is a (111) plane or a plane equivalent to the (111) plane is coated with a (100) plane or the (100) plane.
a step of forming a step consisting of a plane equivalent to a plane and a non-(1QO) plane by etching with a directional particle beam; Matching 1 (lattice constant of the first semiconductor) - (second
(lattice constant of the first semiconductor) |/(lattice constant of the first semiconductor)
The method comprises the steps of growing a layer of the second semiconductor having a thickness of 10 or more, and a step of growing a layer of the first semiconductor on the substrate.

もう一つの発明は、上述の問題点を解決するため表面が
(111)面あるいは前記(111)面と等価な面であ
るG a A s基板と、前記G a A s基板上に
形成された第1クラッド層と、前記第1クラッド層上に
形成され、G a A s層とI n A s量子井戸
細線の界面が少なくとも(100)面あるいは前記(1
00)面と等価な面である前記G a A s層と前記
G a A s層で埋め込まれた前記1nAsnAs量
子線からなる活性層と、前記活性層上に形成された第2
クラッド層からなる構成を備えた量子井戸細線レーザで
ある。
Another invention provides a GaAs substrate whose surface is a (111) plane or a plane equivalent to the (111) plane, and a GaAs substrate formed on the GaAs substrate to solve the above-mentioned problems. a first cladding layer formed on the first cladding layer, the interface between the GaAs layer and the InAs quantum well wire is at least in the (100) plane or in the (100) plane;
a second active layer formed on the active layer;
This is a quantum well thin wire laser with a structure consisting of a cladding layer.

作  用 本発明は、表面が(111)而あるいは前記(111)
面と等価な面である第1の半導体基板上に(100)面
あるいは前記(100)面と等価な面からなる段差の形
成手段として、方向性を持つ粒子線を用いているので、
粒子線の照射方向をある一定角度に保つだけで数百へ以
下の段差が制御性良く得られる。(100)而あるいは
前記(100)面と等価な面および非(100)面から
なる段差に対しても同様に制御性良く得られる。
Effect of the present invention The surface is (111) or (111)
Since a directional particle beam is used as a means for forming a step consisting of a (100) plane or a plane equivalent to the (100) plane on the first semiconductor substrate, which is a plane equivalent to the (100) plane,
By simply keeping the irradiation direction of the particle beam at a certain angle, steps of several hundred or less can be obtained with good controllability. Good controllability can also be obtained for a step formed by a (100) plane or a plane equivalent to the (100) plane and a non-(100) plane.

また第1の半導体基板上に第1の半導体の層あるいは第
2の半導体の層を成長させる場合、第1の半導体の層の
成長ではいずれの面方位をも・つ前記基板表面に対して
ほぼ同じ成長速度で前記第1の半導体の層の単結晶が成
長するのに対し、第2の半導体の層の成長では格子不整
合が10−2以上であるため、前記半導体基板表面の(
100)面上で最も速い成長速度で前記第2の半導体の
層の単結晶が成長し、前記基板表面の面方位が(100
)面からずれるに従い急速に成長速度が低下するという
現象がある。この現象を利用した本発明は、(1o○)
面からなる段差を設けた(111)面をもつ第1の半導
体からなる基板上に第2の半導体の層の成長と第1の半
導体の層の成長を行えば、前記(100)面上にのみ第
2の半導体の層を選択成長させることができ、前記第2
の半導体の層を前記第1の半導体の層で埋め込むことが
できる。
In addition, when growing a first semiconductor layer or a second semiconductor layer on a first semiconductor substrate, the growth of the first semiconductor layer is performed approximately with respect to the surface of the substrate with either plane orientation. While the single crystal of the first semiconductor layer grows at the same growth rate, the lattice mismatch in the growth of the second semiconductor layer is 10-2 or more.
The single crystal of the second semiconductor layer grows at the fastest growth rate on the (100) plane, and the plane orientation of the substrate surface is (100).
) There is a phenomenon in which the growth rate rapidly decreases as the surface deviates from the plane. The present invention utilizing this phenomenon is (1o○)
If a second semiconductor layer and a first semiconductor layer are grown on a substrate made of a first semiconductor having a (111) plane with a step formed by a plane, a layer of the second semiconductor and a first semiconductor layer are grown on the (100) plane. Only the second semiconductor layer can be selectively grown;
A layer of semiconductor may be embedded with the layer of first semiconductor.

もう一つの発明は、上記の量子井戸細線の製造方法を用
いて、数百へ以下の量子井戸細線の幅をもつ活性層が制
御性良く作れる。まだ(111)表面からなるGaAs
基板上には、少なくとも(100)面からなる段差を有
するため、量子井戸細線の面が(oll)面あるいはこ
れと等価な面となり、共振器を容易にへき開によシ形成
することができる。さらにInAsとG a A sの
組合せでは、例えばG a A sとAI xGa 1
−、As 等の組合せに比べて1.1eVの大きなエネ
ルギーギャップ差を有するため、量子井戸効果による半
導体レーザの特性がかなり向上し、さらに発光波長領域
を広く取れる。
Another invention is that an active layer having a width of several hundred or less quantum well wires can be produced with good control using the method for manufacturing quantum well wires described above. GaAs still consists of (111) surface
Since the substrate has a step formed of at least the (100) plane, the plane of the quantum well thin wire becomes the (oll) plane or an equivalent plane, and the resonator can be easily formed by cleavage. Furthermore, in the combination of InAs and Ga As, for example, Ga As and AI x Ga 1
Since it has a large energy gap difference of 1.1 eV compared to a combination of -, As, etc., the characteristics of the semiconductor laser due to the quantum well effect are considerably improved, and the emission wavelength range can be widened.

実施例 (実施例1) 第1図に本発明の一実施例における量子井戸細線の製造
方法の工程図を示す。第1図(a)に示すように、表面
が(711)面からなるG a A s基板4上に、〔
011〕方向に沿って直線からなる開口端を有するエツ
チングマスク8を形成する。マスク8としては、S 1
02薄膜、レジスト等を用いることができる。次にCl
イオンビーム300 等の粒子線によるエツチングを行
なう。第1図中)に示すように、その粒子線の傾き角θ
は、(Oll)面においてG a A s基板の(11
1)面の法線方向から第1図紙面上布回りに36°とす
る。これにより、エッチ側面が(100)面である段差
200を前記G a A s基板4上に形成することが
できる。
Example (Example 1) FIG. 1 shows a process diagram of a method for manufacturing a quantum well thin wire according to an example of the present invention. As shown in FIG. 1(a), on a GaAs substrate 4 whose surface is a (711) plane,
An etching mask 8 having a linear opening end along the [011] direction is formed. As the mask 8, S 1
02 thin film, resist, etc. can be used. Next, Cl
Etching is performed using a particle beam such as an ion beam 300. As shown in Figure 1), the inclination angle θ of the particle beam
is the (11
1) Set the distance from the normal direction of the surface to 36 degrees around the cloth on the paper surface of Figure 1. Thereby, a step 200 whose etched side surface is a (100) plane can be formed on the GaAs substrate 4.

後の工程で量子井戸細線の幅となるエッチ側面の幅D1
は、粒子線によるエツチングにおけるエッチレートから
一義的に決まシ、数百Å以下の値が制御性良く容易に得
られる。例えばG a A sに対して600人/mm
のエッチ速度を使用すれば、30秒のエツチングでG 
a A s基板4上に250人の前記幅りが得られた。
Width D1 of the etch side surface, which becomes the width of the quantum well thin line in a later process
is determined uniquely from the etch rate in particle beam etching, and a value of several hundred Å or less can be easily obtained with good controllability. For example, 600 people/mm for Ga As
If you use the etch speed of 30 seconds, G
250 said widths were obtained on the aAs substrate 4.

第3図に示すように、分子線エピタキシャル成長法を用
いたG a A sとInAs成長速度のG a A 
s基板面方位依存性を示す。G a A g基板面方位
が(100)面からずれるに従って急速にInAsの成
長速度は低下し、(311)面。
As shown in FIG. 3, the G a A s using the molecular beam epitaxial growth method and the G a A
sSubstrate surface orientation dependence. As the G a A g substrate plane orientation deviates from the (100) plane, the growth rate of InAs decreases rapidly, and the growth rate of InAs decreases to the (311) plane.

(111)面等でにほとんど成長は見られなかった。一
方G a A sの成長速度は、いずれの面方位に対し
てもほぼ一定であった。この時の成長条件は、成長温度
550℃、A84/In7ラツクス比6 、 As 4
圧力(フラックス量) 2 X 10−” Torrで
ある。
Almost no growth was observed on the (111) plane. On the other hand, the growth rate of GaAs was almost constant for any surface orientation. The growth conditions at this time were: growth temperature 550°C, A84/In7 lux ratio 6, As4
The pressure (flux amount) is 2×10-” Torr.

一般に第1の半導体と第2の半導体との格子不整合1(
第1の半導体の格子定数)−(第2の半導体の格子定数
)l/(第1の半導体の格子定数)が10−2以上であ
る場合、上記の現象が見られる。G a A sとIn
As成長速度のG a A s基板面方位依存性を利用
して、第1図(c)に示すように、(100)面を持つ
段差を設けた前記(111)面のG a A s基板4
上に分子線エピタキシャル成長法によりInAgnAg
全11部のみに選択成長を行なうことができる。
Generally, the lattice mismatch 1 (
When the ratio (lattice constant of the first semiconductor)−(lattice constant of the second semiconductor) l/(lattice constant of the first semiconductor) is 10 −2 or more, the above phenomenon is observed. G a As and In
Utilizing the dependence of the As growth rate on the Ga As substrate surface orientation, the Ga As substrate with the (111) plane provided with a step having the (100) plane was grown as shown in FIG. 1(c). 4
InAgnAg was deposited on top by molecular beam epitaxial growth method.
Selective growth can be performed only on all 11 parts.

InAsnAs全11成長をするため、原料として金属
Inから作られる原子線In9と金属砒素から作られる
分子線AB410を用いた。
In order to grow all 11 InAsnAs, atomic beam In9 made from metal In and molecular beam AB410 made from metal arsenic were used as raw materials.

次に第1図(d)に示すように、InAs成長と同様に
分子線エピタキシャル成長法によ!1lGaAs層13
をG a A s基板4上に成長させると、G a A
 s層13は第3図に示したように全ての面のG a 
A s基板に対してほぼ同じ成長速度で成長し、InA
snAs上にも前記成長速度とほぼ同じ成長速度で成長
するため、InAs層11をG a A s層13で埋
め込むことができ、層11よりなる量子井戸細線2を形
成することができる。G a A s層13を成長する
ため、原料として金属Gaから作られる原子線Ga12
と金属砒素から作られる分子線AB410を用いた。さ
らに第1図(C)および第1図(d)の工程を繰9返す
ことによシ、量子井戸細線2の多層構造を形成すること
ができ、I n A sはG a A sに比ベエネル
ギーギャップが小さいので、InAsを量子井戸層。
Next, as shown in FIG. 1(d), molecular beam epitaxial growth is used, similar to InAs growth! 1lGaAs layer 13
When grown on the G a A s substrate 4, G a A
As shown in FIG. 3, the S layer 13 has Ga on all sides.
It grows at almost the same growth rate as the InA substrate.
Since the InAs layer 11 can be buried with the GaAs layer 13 because it grows on snAs at almost the same growth rate as the growth rate described above, the quantum well thin wire 2 made of the layer 11 can be formed. In order to grow the GaAs layer 13, an atomic beam Ga12 made from metal Ga is used as a raw material.
A molecular beam AB410 made from metal arsenic and metal arsenic was used. Further, by repeating the steps of FIG. 1(C) and FIG. 1(d) nine times, a multilayer structure of the quantum well thin wire 2 can be formed, and I n A s is compared to G a A s. Since the energy gap is small, InAs is used as a quantum well layer.

G a A sをポテンシャル障壁層としだ量子井戸細
線を形成できる。なお本実施例ではInAs成長。
A thin quantum well wire can be formed using GaAs as a potential barrier layer. In this example, InAs is grown.

G a A g成長を分子線エピタキシャル成長に代表
される粒子線を用いて行なったが、有機金属気相成長に
代表される非平衡気相成長を用いて行なっても良い。ま
た分子線A s 4の代わシにA a 2を用いても良
い。
Although G a A g growth was performed using a particle beam typified by molecular beam epitaxial growth, it may also be performed using non-equilibrium vapor phase growth typified by organometallic vapor phase growth. Further, instead of the molecular beam A s 4, A a 2 may be used.

(実施例2) 第2図に本発明の一実施例における量子井戸箱の製造方
法の工程図を示す。第2図(a)に示すように、(11
1)表面からなるG a A g基板4上に、〔o11
〕方向妬沿って正弦波状あるいは鋸波状からなる開口端
を有するエツチングマスク14を形成する。マスク14
としては、S 102薄膜、レジスト等を用いることが
できる。第2図中)に示すように、第1図申)と同様な
C1イオンビーム300等の粒子線によるエツチングを
行ない、エッチ側面が(100)面と非(10o)とか
らなる段差を前記G a A s基板4上に形成するこ
とができる。
(Example 2) FIG. 2 shows a process diagram of a method for manufacturing a quantum well box in an example of the present invention. As shown in Figure 2(a), (11
1) On the G a A g substrate 4 consisting of the surface, [o11
] An etching mask 14 is formed having an opening end in the shape of a sine wave or a sawtooth wave along the direction. mask 14
As the material, S102 thin film, resist, etc. can be used. As shown in Figure 2), etching with a particle beam such as a C1 ion beam 300 similar to that in Figure 1) is performed to form a step with the etched side surface consisting of a (100) plane and a non-(10o) plane. It can be formed on the aAs substrate 4.

後の工程により量子井戸箱の一つの幅となるエッチ側面
の幅D2は、前記幅D1  と同様に粒子線によるエツ
チングにおけるエッチレートから一義的に決まり、数百
へ以下の値が制御性良く容易に得られる。一方、量子井
戸箱の幅D3の方向と垂直に交わるInAs層11の断
面形状は、マスク14の開口端形状に決定する。ま量子
井戸箱の幅D3は例えば(100)接面Aにおける曲率
半径に依存し、曲率半径が大きい程D3は長くなる。量
子井戸箱の幅D4は、InAs  の成長時間により決
定できる。第2図(c)に示すように、第1図(c)の
工程と同様にInAs層11の選択成長を行ない。次に
第2図(d)に示すように、第1図(d)の工程と同様
にG a A s層13を形成することができる。さら
に第2図(C)および第2図(d)の工程を繰り返すこ
とにより、量子井戸箱3の多層構造を形成するととがで
きる。
The width D2 of the etched side surface, which becomes one width of the quantum well box in the later process, is uniquely determined from the etch rate in particle beam etching, similar to the width D1, and a value of several hundred or less can be easily controlled with good controllability. can be obtained. On the other hand, the cross-sectional shape of the InAs layer 11 perpendicular to the direction of the width D3 of the quantum well box is determined by the shape of the opening end of the mask 14. The width D3 of the quantum well box depends, for example, on the radius of curvature at the (100) tangent surface A, and the larger the radius of curvature, the longer D3 becomes. The width D4 of the quantum well box can be determined by the growth time of InAs. As shown in FIG. 2(c), the InAs layer 11 is selectively grown in the same manner as in the step of FIG. 1(c). Next, as shown in FIG. 2(d), a GaAs layer 13 can be formed in the same manner as in the step of FIG. 1(d). Further, by repeating the steps shown in FIG. 2(C) and FIG. 2(d), a multilayer structure of the quantum well box 3 can be formed.

(実施例3) 第4図に本発明の一実施例における量子井戸細線レーザ
の製造方法の工程図を示す。第4図(a)に示すように
、(111)表面からなるn形G a A s基板15
上にn形AlGaAs 16からなる第1のクラッド層
を成長する。第4図(b)に示すように、G a A 
s層17を成長する。次に第1図(a)〜(d)の工程
を施すことにより第4図(c)に示すような単一で離散
的なInAs量子井戸細線18をもつ活性層19が得ら
れる。さらに第1図(C)、 (d)の工程を2回縁シ
返すと第4図(d)に示すような群を成し、離散的なI
nAs量子井戸細線18をもつ活性層20が得られる。
(Example 3) FIG. 4 shows a process diagram of a method for manufacturing a quantum well thin wire laser according to an example of the present invention. As shown in FIG. 4(a), an n-type GaAs substrate 15 having a (111) surface
A first cladding layer of n-type AlGaAs 16 is grown thereon. As shown in FIG. 4(b), G a A
The s-layer 17 is grown. Next, by performing the steps shown in FIGS. 1(a) to 1(d), an active layer 19 having a single, discrete InAs quantum well thin wire 18 as shown in FIG. 4(c) is obtained. Furthermore, if the steps in Fig. 1(C) and (d) are repeated twice, a group as shown in Fig. 4(d) is formed, and a discrete I
An active layer 20 having nAs quantum well wires 18 is obtained.

次に第4図(、)に示すようにp形A I G a A
 s21からなる第2のクラッド層を成長し、AlZn
22からなるp形電極およびAuGe23からなるn形
電極を形成するとn形G a A s基板16上に第1
のクラッド層、InAs量子井戸細線18およびG a
 A s層17からなる活性層19.第2のクラッド層
を積層した量子井戸細線レーザが得られる。
Next, as shown in Fig. 4(,), the p-type A I G a A
Grow a second cladding layer consisting of s21 and AlZn
When a p-type electrode made of 22 and an n-type electrode made of AuGe 23 are formed, a first
cladding layer, InAs quantum well wire 18 and Ga
Active layer 19 consisting of As layer 17. A quantum well thin wire laser in which the second cladding layer is laminated is obtained.

また、(111)表面からなるG a A s基板15
上には、(10o)面からなる段差を有するため、In
As量子井戸細線18の段面が(oll)面あるいはこ
れと等価な面となり、共振器を容易にへき開により形成
することができる。なお本実施例ではG a A s基
板とInAs量子井戸細線とAlGaAsクラッド層を
用いたが以下の表の組み合わせでも良い。
In addition, a GaAs substrate 15 having a (111) surface
Since there is a step formed by the (10o) plane on the top, In
The step plane of the As quantum well wire 18 becomes an (oll) plane or an equivalent plane, and a resonator can be easily formed by cleaving. In this embodiment, a GaAs substrate, an InAs quantum well thin wire, and an AlGaAs cladding layer are used, but the combinations shown in the table below may be used.

発明の効果 以上の説明から明らかなように、本発明は、基板表面が
(111)面である第1の半導体基板上に側面が(10
o)而からなる段差の形成手段として、方向性を持つ粒
子線を用いているので、粒子線の照射方向をある一定角
度に保つだけで数百へ以下の段差が制御性良く得られる
。(10o)面あるいは前記(100)面と特価な面お
よび非(100)面からなる段差に対しても同様に制御
性良く得られる。また第1の半導体よりなる基板上に第
2の半導体あるいは第1の半導体の層を成長させる場合
、第1の半導体の層成長ではいずれの面方位をもつ前記
基板表面に対して、はぼ同じ成長速度で前記第1の半導
体の層の単結晶が成長するのに対し、第2の半導体の層
成長では格子不整合が10 以上であるため、前記基板
表面の(100)面上で最も速い成長速度で前記第2の
半導体の層の単結晶が成長し、前記基板表面の面方位が
(100)面からずれるに従い急速に成長速度が低下す
るという現象がある。この現象を利用した本発明は、(
100)面からなる段差を設けた(111)面をもつ第
1の半導体からなる基板上に第2の半導体の層の成長と
第1の半導体の層の成長を行えば、前記(100)面上
にのみ第2の半導体の層を選択成長させることができ、
前記第2の半導体の層を前記第1の半導体の層で埋め込
むことができる。
Effects of the Invention As is clear from the above description, the present invention provides a first semiconductor substrate whose surface is a (111) plane, and a side surface of which is a (10) plane.
o) Since a directional particle beam is used as the means for forming the step, a step of several hundred or less can be obtained with good controllability simply by keeping the irradiation direction of the particle beam at a certain angle. Good controllability can also be obtained for a step formed from the (10o) plane or the above-mentioned (100) plane, a special plane, or a non-(100) plane. In addition, when growing a second semiconductor or a layer of the first semiconductor on a substrate made of a first semiconductor, the growth of the first semiconductor layer has approximately the same orientation with respect to the surface of the substrate having either plane orientation. Whereas the single crystal of the first semiconductor layer grows at a growth rate, the growth rate of the second semiconductor layer is fastest on the (100) plane of the substrate surface because the lattice mismatch is 10 or more. There is a phenomenon in which the single crystal of the second semiconductor layer grows at a certain growth rate, and the growth rate rapidly decreases as the plane orientation of the substrate surface deviates from the (100) plane. The present invention, which utilizes this phenomenon, (
If a second semiconductor layer and a first semiconductor layer are grown on a substrate made of a first semiconductor having a (111) plane with a step formed by a (100) plane, the (100) plane A second semiconductor layer can be selectively grown only on the top,
The second semiconductor layer can be embedded with the first semiconductor layer.

明 もう一つの発子は、上記の量子井戸細線の製造方法を用
いて、数百へ以下の量子井戸細線の幅をもつ活性層が制
御性良く作れる。また(111)表面からなるGaA 
s基板上には、少なくとも(100)面からなる段差を
有するため、量子井戸細線の断面が(011)面あるい
はこれと等価な面となり、共振器を容易にへき開により
形成することができる。さらにInAsとGaA sの
組合せでは、例えばG a A sとA1工G a 1
−xAs等の組合せに比べて1.1eVの大きなエネル
ギーギャップ差を有するだめ、量子井戸効果による半導
体レーザの特性がかなり向上し、さらに発光波長領域を
広く取れる。
Another advantage is that by using the above-described method for manufacturing quantum well wires, active layers having a width of several hundred or less quantum well wires can be fabricated with good controllability. Also, GaA consisting of (111) surface
Since the s-substrate has a step formed of at least a (100) plane, the cross section of the quantum well thin wire becomes a (011) plane or an equivalent plane, and a resonator can be easily formed by cleavage. Furthermore, in the combination of InAs and GaAs, for example, GaAs and A1
Since it has a large energy gap difference of 1.1 eV compared to a combination such as -xAs, the characteristics of the semiconductor laser due to the quantum well effect are considerably improved, and the emission wavelength range can be widened.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(、)〜(d)は本発明の一実施例における量子
井戸細線の製造方法を示す工程図、第2図(a)〜(d
)は本発明の一実施例における量子井戸箱の製造方法を
示す工程図、第3図はG a A gとInAs成長速
度のG a A s基板面方位依存性を示す特性図、第
4図(、)〜(、)は本発明の一実施例における量子井
戸細線レーザの製造方法を示す工程図、第5図(−)は
量子井戸構造の概念図、第5図(b)は量子井戸構造の
状態密度を示す特性図、第5図(、)は量子井戸細線の
概念図、第5図(b)は量子井戸細線の状態密度を示す
特性図、第7図(、)は量子井戸箱の概念図、第7図(
b)は量子井戸箱の状態密度を示す特性図、第8図(a
)〜(C)は従来例の量子井戸細線の製造方法を示す工
程図、第9図(a)〜(C)は従来例の量子井戸箱の製
造方法を示す工程図である。 2・・・・・・量子井戸細線、3・・・・・・量子井戸
箱、4・・・・・G a A s基板、8,14・・・
・・・エツチングマスク、9・・・・・・In、10・
・・・・・As4.11・・・・・・InAs層、12
・++−++Ga、 13.17===GaAs層、1
5 ・−・−・−n形GaAs基板、16−・−n形A
lGaAs 、 18・・・・・・InAg量子井戸細
線、19.20・・・・・・活性層、21 =−−p形
A I G a A s、22−=・AuZn 、 2
3・・・・・・AuGe0 代理人の氏名 弁理士 粟 野 重 孝 ほか1名第 
1 因 2 (If) 量菩斤戸部謀 lZ−Q山 図 3(fυ・−量各庁一箱 4□−(?a、ハS基板 9−1代 lθ゛−As4 H・−工IPLA”;M /Z−G山 42図 図 (Lay ) (10θ)(71υA  (3/l)ハ       
 (fff)AORIENTATION ((ra、ハS基板面゛方°侃〕 成長A度:sso’c フラ・ンクスエヒ(八s+/(ra) −3フラッグス
R,<A34/ IfL) : 5AS4五力(フラツ
クス量、):zxtoTρとど4−−− (ta−As
Z板 14−  エツチングマス7 3ρθ゛−イτンヒーム 15 ’−77’thenAs基板 16−n% AI (ra、ハS 77−tGαA8層 /8−−1mASiJ叶戸3目碌 ■〔oIT)方向 l5”−7’−杉Q(LA S基板 /6− nW4 AdtktAs /7−6aAS層 /B−1偽ハS量+叶戸3TE !& /VZθ−゛り各村り肩 2/−PわA)4−a A 5 22−一′ハLLlLrL ’13−ALL(3−己 耽幻仄厄2攬 既豹扶旭ffi度ρ(す 第 図 第 図
FIGS. 1(a) to (d) are process diagrams showing a method for manufacturing a quantum well thin wire according to an embodiment of the present invention, and FIGS. 2(a) to (d)
) is a process diagram showing a method for manufacturing a quantum well box in an embodiment of the present invention, FIG. 3 is a characteristic diagram showing the dependence of GaAg and InAs growth rate on GaAs substrate surface orientation, and FIG. (,) to (,) are process diagrams showing a method for manufacturing a quantum well thin wire laser in an embodiment of the present invention, FIG. 5(-) is a conceptual diagram of the quantum well structure, and FIG. 5(b) is a quantum well Characteristic diagram showing the density of states of the structure. Figure 5 (,) is a conceptual diagram of a quantum well wire. Figure 5 (b) is a characteristic diagram showing the density of states of a quantum well wire. Figure 7 (,) is a diagram of a quantum well wire. Conceptual diagram of the box, Figure 7 (
b) is a characteristic diagram showing the density of states of a quantum well box, and Fig. 8(a)
) to (C) are process diagrams showing a conventional method for manufacturing a quantum well thin wire, and FIGS. 9(a) to (C) are process diagrams showing a conventional method for manufacturing a quantum well box. 2...Quantum well thin wire, 3...Quantum well box, 4...GaAs substrate, 8,14...
...Etching mask, 9...In, 10.
...As4.11 ...InAs layer, 12
・++−++Ga, 13.17===GaAs layer, 1
5 ・-・-・-n-type GaAs substrate, 16-・-n-type A
lGaAs, 18...InAg quantum well thin wire, 19.20...Active layer, 21 =--p type AIGaAs, 22-=・AuZn, 2
3...AuGe0 Name of agent Patent attorney Shigetaka Awano and 1 other person
1 Cause 2 (If) Quantity Bodhisattva Tobe 1Z-Q mountain figure 3 (fυ・-Quantity each office 1 box 4□-(?a, HaS board 9-1 generation lθ゛-As4 H・-Eng IPLA” ;M/Z-G mountain 42 diagram (Lay) (10θ) (71υA (3/l)
(fff) AORIENTATION ((ra, S substrate surface゛° direction) Growth A degree: sso'c Fra nxuehi (8s+/(ra) -3 flags R, <A34/ IfL): 5AS4 five forces (flux Quantity, ): zxtoTρ and 4--- (ta-As
Z plate 14-Etching mass 7 3ρθ゛-Iτenheam 15'-77'thenAs substrate 16-n% AI (ra, HaS 77-tGαA8 layer/8--1mASiJ Kano door 3rd order ■ [oIT) direction l5 "-7'-Sugi Q (LA S board/6-nW4 AdtktAs/7-6a AS layer/B-1 false Ha S amount + Kanoto 3TE! & /VZθ-゛ri each village shoulder 2/-PwaA ) 4-a A 5 22-1'HALLlLrL '13-ALL

Claims (9)

【特許請求の範囲】[Claims] (1)表面が(111)面あるいは前記(111)面と
等価な面である第1の半導体よりなる基板上に(100
)面あるいは前記(100)面と等価な面からなる段差
を方向性を持つ粒子線によるエッチングで形成する工程
と、前記基板の前記段差部に前記第1の半導体と第2の
半導体との格子不整合|(第1の半導体の格子定数)−
(第2の半導体の格子定数)|/(第1の半導体の格子
定数)が10^−^2以上である前記第2の半導体の層
を成長させる工程と、前記基板上に前記第1の半導体の
層を成長させる工程からなる量子井戸細線の製造方法。
(1) On a substrate made of a first semiconductor whose surface is a (111) plane or a plane equivalent to the (111) plane,
) plane or a plane equivalent to the (100) plane by etching with a directional particle beam, and forming a lattice of the first semiconductor and the second semiconductor in the step part of the substrate. Mismatch | (lattice constant of first semiconductor) −
(lattice constant of the second semiconductor) |/(lattice constant of the first semiconductor) of growing the second semiconductor layer of 10^-^2 or more; A method for manufacturing a quantum well thin wire, which consists of a step of growing a semiconductor layer.
(2)第2の半導体の層を分子線エピタキシャル成長に
代表される粒子線を用いて成長させる工程からなる特許
請求の範囲第1項記載の量子井戸細線の製造方法。
The method for manufacturing a quantum well thin wire according to claim 1, which comprises the step of (2) growing the second semiconductor layer using a particle beam typified by molecular beam epitaxial growth.
(3)第2の半導体の層を有機金属気相成長に代表され
る非平衡気相成長を用いて成長させる工程からなる特許
請求の範囲第1項記載の量子井戸細線の製造方法。
(3) The method for manufacturing a quantum well thin wire according to claim 1, which comprises the step of growing the second semiconductor layer using non-equilibrium vapor phase epitaxy typified by organometallic vapor phase epitaxy.
(4)第1の半導体はGaAsであり、第2の半導体は
InAsである特許請求の範囲第1項記載の量子井戸細
線の製造方法。
(4) The method for manufacturing a quantum well thin wire according to claim 1, wherein the first semiconductor is GaAs and the second semiconductor is InAs.
(5)表面が(111)面あるいは前記(111)面と
等価な面である第1の半導体よりなる基板上に(100
)面あるいは前記(100)面と等価な面および非(1
00)面からなる段差を方向性を持つ粒子線によるエッ
チングで形成する工程と、前記基板の前記段差部に前記
第1の半導体と第2の半導体との格子不整合|(第1の
半導体の格子定数)−(第2の半導体の格子定数)|/
(第1の半導体の格子定数)が10^−^2以上である
前記第2の半導体の層を成長させる工程と、前記基板上
に前記第1の半導体の層を成長させる工程からなる量子
井戸箱の製造方法。
(5) On a substrate made of a first semiconductor whose surface is a (111) plane or a plane equivalent to the (111) plane,
) plane or a plane equivalent to the (100) plane and non-(1
00) plane by etching with a directional particle beam, and forming a lattice mismatch between the first semiconductor and the second semiconductor in the step part of the substrate. lattice constant) - (lattice constant of second semiconductor) |/
A quantum well comprising a step of growing a layer of the second semiconductor whose lattice constant (lattice constant of the first semiconductor) is 10^-^2 or more, and a step of growing a layer of the first semiconductor on the substrate. How to make a box.
(6)第2の半導体の層を分子線エピタキシャル成長に
代表される粒子線を用いて成長させる工程からなる特許
請求の範囲第5項記載の量子井戸箱の製造方法。
(6) The method for manufacturing a quantum well box according to claim 5, which comprises the step of growing the second semiconductor layer using a particle beam typified by molecular beam epitaxial growth.
(7)第2の半導体の層を有機金属気相成長に代表され
る非平衡気相成長を用いて成長させる工程からなる特許
請求の範囲第5項記載の量子井戸箱の製造方法。
(7) The method for manufacturing a quantum well box according to claim 5, which comprises the step of growing the second semiconductor layer using non-equilibrium vapor phase epitaxy typified by organometallic vapor phase epitaxy.
(8)第1の半導体はGaAsであり、第2の半導体は
InAsであることを特徴とする特許請求の範囲第5項
記載の量子井戸箱の製造方法。
(8) The method for manufacturing a quantum well box according to claim 5, wherein the first semiconductor is GaAs and the second semiconductor is InAs.
(9)表面が(111)面あるいは前記(111)面と
等価な面であるGaAs基板と、前記GaAs基板上に
形成された第1クラッド層と、前記第1クラッド層上に
形成され、GaAs層とInAs量子井戸細線の界面が
少なくとも(100)面あるいは前記(100)面と等
価な面である前記GaAs層と前記GaAs層で埋め込
まれた前記InAs量子井戸細線からなる活性層と、前
記活性層上に形成された第2クラッド層からなる量子井
戸細線レーザ。
(9) a GaAs substrate whose surface is a (111) plane or a plane equivalent to the (111) plane, a first cladding layer formed on the GaAs substrate, and a GaAs substrate formed on the first cladding layer; an active layer consisting of the GaAs layer and the InAs quantum well wire embedded in the GaAs layer, wherein the interface between the layer and the InAs quantum well wire is at least a (100) plane or a plane equivalent to the (100) plane; A quantum well thin wire laser consisting of a second cladding layer formed on top of the second cladding layer.
JP25511988A 1988-10-11 1988-10-11 Manufacture of quantum well fine wire and quantum well box and quantum well fine wire laser Pending JPH02101784A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25511988A JPH02101784A (en) 1988-10-11 1988-10-11 Manufacture of quantum well fine wire and quantum well box and quantum well fine wire laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25511988A JPH02101784A (en) 1988-10-11 1988-10-11 Manufacture of quantum well fine wire and quantum well box and quantum well fine wire laser

Publications (1)

Publication Number Publication Date
JPH02101784A true JPH02101784A (en) 1990-04-13

Family

ID=17274355

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH02101784A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04186848A (en) * 1990-11-21 1992-07-03 Nec Corp Manufacture of field effect transistor
JPH05167187A (en) * 1991-12-13 1993-07-02 Nec Corp Semiconductor laser
JPH06260427A (en) * 1993-03-05 1994-09-16 Nec Corp Selective growth method of semiconductor film
JPH06283482A (en) * 1993-03-26 1994-10-07 Nec Corp Forming method of fine structure
KR100379617B1 (en) * 2001-03-26 2003-04-10 한국과학기술연구원 Method of forming quantum dot array using tilted substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04186848A (en) * 1990-11-21 1992-07-03 Nec Corp Manufacture of field effect transistor
JPH05167187A (en) * 1991-12-13 1993-07-02 Nec Corp Semiconductor laser
JPH06260427A (en) * 1993-03-05 1994-09-16 Nec Corp Selective growth method of semiconductor film
JPH06283482A (en) * 1993-03-26 1994-10-07 Nec Corp Forming method of fine structure
KR100379617B1 (en) * 2001-03-26 2003-04-10 한국과학기술연구원 Method of forming quantum dot array using tilted substrate

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