JPS637671A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS637671A JPS637671A JP61150676A JP15067686A JPS637671A JP S637671 A JPS637671 A JP S637671A JP 61150676 A JP61150676 A JP 61150676A JP 15067686 A JP15067686 A JP 15067686A JP S637671 A JPS637671 A JP S637671A
- Authority
- JP
- Japan
- Prior art keywords
- buried
- zener
- supply terminal
- current supply
- zener diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 208000019300 CLIPPERS Diseases 0.000 description 1
- 208000021930 chronic lymphocytic inflammation with pontine perivascular enhancement responsive to steroids Diseases 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、埋込ツェナ・ダイオードを構成−素子とす
る回路を備えた半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device including a circuit whose constituent elements are buried Zener diodes.
ツェナ・ダイオードは、定電圧回路、電源回路、クリッ
パ回路、保護回路などに広く筐用されているＯ
Ｐ＋領域、帥領域を拡散で形成したツェナ・り゛イオー
ドでは、表面でブＶ−クタ９ウンを生ずるために、ドリ
フト、ノイズが多い。Zener diodes are widely used in constant voltage circuits, power supply circuits, clipper circuits, protection circuits, etc. In Zener diodes, in which the OP+ region and the cross region are formed by diffusion, the surface of the Zener diode is There is a lot of drift and noise due to the noise.
この欠点を除くために、従来、接合部を埋込構造とする
方法が採られることがある。In order to eliminate this drawback, a method has conventionally been adopted in which the joint is made into an embedded structure.
従来のインブラントを用いる埋込ツェナ・ダイオードは
、シリーズ抵抗が大きくなり、電圧安定度が悪い。また
、ツェナ電流制限抵抗は埋込ツェナ・ダイオードのアイ
ランドと別個の領域に配置する構造のために、チップ面
積が大きくなるという問題があった。Recessed Zener diodes using conventional implants have high series resistance and poor voltage stability. Furthermore, since the Zener current limiting resistor is arranged in a region separate from the island of the buried Zener diode, there is a problem in that the chip area becomes large.
この発明は、上記問題を解消するためになされたもので
、安定度がよく、チップ面積を小さくできる埋込ツェナ
・ダイオードを構成−素子とする回路を備えた半導体装
置を提供することを目的とする。The present invention was made in order to solve the above problems, and an object of the present invention is to provide a semiconductor device equipped with a circuit having a buried Zener diode as a constituent element, which has good stability and can reduce the chip area. do.
この発明の半導体装置は、上記目的を達成するために、
アイランド内に埋込層の一部に接合するアイソレーショ
ン領域を形成して埋込ツェナ・ダイオτドを構成し、同
一アイランド内に上記埋込ツェナ・ダイオードの電流供
給端子と電圧出力端子 −を設け、ツェナ電流制限抵抗
を
上記電流供給端子と埋込層の間のエピタキシャル層の抵
抗による構造としたものである。In order to achieve the above object, the semiconductor device of the present invention has the following features:
A buried Zener diode is formed by forming an isolation region connected to a part of the buried layer within the island, and a current supply terminal and a voltage output terminal of the buried Zener diode are connected within the same island. A zener current limiting resistor is provided and has a structure based on a resistance of an epitaxial layer between the current supply terminal and the buried layer.
第１図（ａ） 、 （ｂ）はこの発明の一実施例を示す
平面図、断面図、第２図は第１図（ａ） 、 （ｂ）に
示す部分の等価回路を示す回路図である。FIGS. 1(a) and (b) are a plan view and a sectional view showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an equivalent circuit of the portion shown in FIGS. 1(a) and (b). be.
図において１はＮ＋埋込層、２はＮエピタキシャル層、
３はＰ アイソレーション領域、４は耐埋込層の一部に
接合するＰ＋アイソレーション領域、５．６は耐拡散領
域、７は保護膜、８は電流供給端子、９は電圧出力端子
、１０は埋込ツェナ・ダイオード、１１はツェナ電流制
限抵抗、１２は寄生抵抗である。In the figure, 1 is an N+ buried layer, 2 is an N epitaxial layer,
3 is a P isolation region, 4 is a P+ isolation region connected to a part of the anti-buried layer, 5.6 is an anti-diffusion region, 7 is a protective film, 8 is a current supply terminal, 9 is a voltage output terminal, 10 is a buried Zener diode, 11 is a Zener current limiting resistor, and 12 is a parasitic resistor.
Ｐ＋アイソレーション領域４とＮ＋埋込層１で、Ａ部分
でジャンクションブレークダウンを生ずる埋込ツェナ・
ダイオード１０が形成され、Ｐアイル−ジョン領域３で
囲われたアイランド内に電流供給端子８、電圧出力端子
９を設けると、電流供給端子８とＮ＋埋込層１の間のＮ
エピタキシャル層２の抵抗Ｒｚｌｌ がツェナ電流を
制限することになる。電圧出力端子９側にできる寄生抵
抗Ｒｏ１２は、高いインピーダンスで受ければ、電圧降
下は無視できる。The P+ isolation region 4 and the N+ buried layer 1 have a buried zener that causes junction breakdown in the A section.
When a current supply terminal 8 and a voltage output terminal 9 are provided in an island in which a diode 10 is formed and surrounded by a P aisle region 3, an N voltage between the current supply terminal 8 and the N+ buried layer 1 is
The resistance Rzll of the epitaxial layer 2 will limit the Zener current. If the parasitic resistance Ro12 formed on the voltage output terminal 9 side is received with high impedance, the voltage drop can be ignored.
この構造では、埋込部分でブレークダウンを生ずるため
に、低ドリフト、低ノイズとなるとともに、ツェナ電流
制限抵抗を埋込ツェナ・ダイオードと同一のアイランド
内にとったので、チップ面積が小さくなる。In this structure, breakdown occurs in the buried portion, resulting in low drift and low noise, and since the Zener current limiting resistor is placed in the same island as the buried Zener diode, the chip area is reduced.
また、埋込ツェナ・ダイオードを埋込層とアイソレーシ
ョン領域で形成したので、特別にプロセス工程が増大す
るということがない。Furthermore, since the buried Zener diode is formed using the buried layer and the isolation region, there is no need for an extra increase in process steps.
この発明によれば、以上のとおシ、プロセス工程を増や
すことなく、低ドリフト、低ノイズを実現することがで
き、かつ、ツェナ電流制限抵抗を埋込ツェナ・ダイオー
ドと同一のアイランド内にとったので、チップ面積が小
きくなるという効果がある。According to the present invention, low drift and low noise can be achieved without increasing the number of process steps, and the Zener current limiting resistor is placed in the same island as the embedded Zener diode. This has the effect of reducing the chip area.
第１図（ａ） 、 （ｂ）はこの発明の一実施例を示す
平面図、断面図、第２図は第１図（ａ） 、 （ｂ）に
示す部分の等価回路を示す回路図である。
１・・耐埋込層、２・・・Ｎエピタキシャル層、３゜４
・・・Ｐ＋アイソレーション領域、５，６・・−耐拡散
領域、７・・保護膜、８・・・電流供給端子、９・・・
電圧出力端子、１０・・・埋込ンエナ・ダイオード、１
１・・・ツェナ電流制限抵抗、１２・・−寄生抵抗。
なお同一符号が同一部分を示す。
特許出願人 新日本無線株式会社
第１図
第２図FIGS. 1(a) and (b) are a plan view and a sectional view showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an equivalent circuit of the portion shown in FIGS. 1(a) and (b). be. 1... Buried resistant layer, 2... N epitaxial layer, 3゜4
...P+ isolation region, 5, 6...-diffusion resistant region, 7... protective film, 8... current supply terminal, 9...
Voltage output terminal, 10...Embedded energy diode, 1
1... Zener current limiting resistance, 12...-parasitic resistance. Note that the same reference numerals indicate the same parts. Patent applicant New Japan Radio Co., Ltd. Figure 1 Figure 2
Claims (1)
ン領域を形成して埋込ツェナ・ダイオードを構成し、該
アイランド内に上記埋込ツェナ・ダイオードの電流供給
端子と電圧出力端子を設けた回路を備えた半導体装置。A circuit in which a buried Zener diode is formed by forming an isolation region connected to a part of a buried layer in an island, and a current supply terminal and a voltage output terminal of the buried Zener diode are provided in the island. A semiconductor device equipped with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150676A JPH0642554B2 (en) | 1986-06-28 | 1986-06-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150676A JPH0642554B2 (en) | 1986-06-28 | 1986-06-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS637671A true JPS637671A (en) | 1988-01-13 |
| JPH0642554B2 JPH0642554B2 (en) | 1994-06-01 |
Family
ID=15502035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61150676A Expired - Fee Related JPH0642554B2 (en) | 1986-06-28 | 1986-06-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642554B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57154879A (en) * | 1981-02-04 | 1982-09-24 | Rca Corp | Semiconductor device |
| JPS60123070A (en) * | 1983-12-08 | 1985-07-01 | Nec Corp | Semiconductor device |
-
1986
- 1986-06-28 JP JP61150676A patent/JPH0642554B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57154879A (en) * | 1981-02-04 | 1982-09-24 | Rca Corp | Semiconductor device |
| JPS60123070A (en) * | 1983-12-08 | 1985-07-01 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0642554B2 (en) | 1994-06-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |