JPS63152173A - Gate turn off thyristor - Google Patents

Abstract

PURPOSE:To increase intercepting capability, and making an external connection wiring for an absorber element unnecessary, by forming, on the same wafer, a surge absorber connected between the gate and the cathode of a GTO device, and growing a P<+> epitaxial layer on the surfaces of a P2 layer and P<+> layer. CONSTITUTION:A P1 layer and a P2 layer having a surface concentration of 2X10<17> are formed by diffusing impurity into an N1 substrate having an impurity concentration of 4X10<13>, and an N5 layer having a surface concentration of 10<19> is formed by diffusing phosphorus into the P2 layer. Then a buried gate of P<+> layer is formed by diffusing boron into the P2 layer, and an oxide film 14 is stuck on a part of the P2 layer surface so as to bridge the N5 layer surface and a P2N5 junction. After that, an P<->2 layer is grown on the P2 layer on which the film 14 does not exist and on the P<+> layer surface by epitaxy applying the film 14. The P<+> layer having a concentration of about 10<18> in the initial growth process is changed to the P2 layer having a surface concentration of 10<16> after the growth, and a sheet resistance necessary for turn off is constituted thereby. In this manner, a GTO is constituted of a main GTO part 1, and an amplification GTO part 2 and a surge absorber part 13 between which the GTO main part is placed. The intercepting capability of this GTO is increased.

Description

[Detailed description of the invention] A. Industrial application field The present invention relates to gate turn-off thyristors.

B0 Summary of the Invention This invention improves the configuration of the surge absorber element connected between the gate and cathode and the configuration of the main gate turn-off thyristor, and creates a nine-gate turn-off thyristor (
(hereinafter abbreviated as GTO element), the surge absorber element connected between the gate and cathode of the GTO element is formed on the same unit.
P+epi Jd f several μm on the side of cP layer and P+ layer
By forming a surge absorber, the interrupting ability can be improved without lowering the pre-down voltage of the surge absorber, and the wiring for the externally connected surge absorber element can be eliminated, thereby reducing surges from the wiring. This eliminates intrusion and also prevents short circuits and disconnections in the wiring.

C6 Prior Art FIG. 5 is an explanatory diagram of the configuration of a GTO element having an amplification gate. In FIG. 5, the main GTO section 1 has P and N parts.

P-N! The amplification section 2 consists of PrN+Pt
Consists of N5. 3 is a cathode electrode of the main GTO section 1, 4 is a gate electrode of the main GTO section 1, 5 is a cathode electrode of the Vi amplification GTO section 2Q, and this cathode electrode 5 is connected to the gate electrode 4 of the main GTO section 1 by a connecting body 6. . 7 is a gate electrode of the amplification section 2; In the figure, G is a gate terminal and a cathode terminal.

8 is an amplifier 07 that does not allow the gate current to flow directly to the main GTO section 1.
9 is a Zener diode that biases the amplifier 070 section 2, and the series body of this Zener diode 9 and diode 8 is connected to the connection body 6.
and is connected to the gate electrode 7 of the amplifier 070 section 2. 10
11 is a diode that ensures that the on-current of the amplifying GTO section 20 flows to the gate of the main GTO section 1 without flowing to the cathode of the main GTO section 10, and 11 is a surge that absorbs energy stored in the inductance due to the wiring of the gate circuit. This is a Zener diode which is an absorber element. The diode 10 and the Zener diode 117) are connected in series between the connection body 6 and the cathode electrode 6.

FIG. 6 is an electrical circuit diagram of FIG. 5, and A in the figure is an anode terminal.

In the buried gate type GTO element configured as shown in FIG. 5, a voltage value of 60 V is normally applied as the gate-off voltage. However, when the GTO element is turned off, an overvoltage of 60 V or more may be applied between the gate G and the cathode. It is known that the cause of this overvoltage is 07t of energy stored in the inductance due to the wiring N of the gate circuit. This ninth,
In the GTO element, the breakdown voltage between the gate G and the cathode is 120
However, if an overvoltage exceeding the withstand voltage is applied, the junction between the gate G and the cathode will be destroyed. Therefore, when an overvoltage occurs between the gate G and the cathode, the Zener diode 11 is activated to absorb the positive portion of the overvoltage and prevent destruction.

D0 Problems to be Solved by the Invention However, since the Zener diode 11, which is a surge absorber element, is entirely connected to the outside, the following problem occurs.

(1) To connect the surge absorber element externally,
Surges occur from the wiring itself, reducing its function as an absorber.

(2) Due to the external connection, there is a risk that the wiring may short out inside the case.

(3) External connection of the surge absorber element complicates the case structure.

(4) The number of man-hours required to assemble the case increases.

(5) The case becomes larger as diodes and the like are housed inside the case.

(6) Since a diode and a Zener diode are connected to the GTO element itself, the p yield decreases due to defects in the connection.

(7) In order to solve the above-mentioned nine problems, it has become possible to form surge absorber elements on the same wafer. As one of these, a configuration is being considered in which a Zener voltage is obtained on the same wafer. However, if such a configuration is adopted, a new problem arises in that the cut-off current of the GTO element is hindered.

Ninth means to solve all problems of E6 This invention forms an independent 7'CNI layer on the surface of the P5 layer where the P+ low resistance layer is formed, and combines all of the different surfaces of this N3 layer with P,
N, an oxide film is formed on the different surface of the P7 layer along a part of the junction, and this oxide film is left to form P, J- and P+ without an oxide film.
p”epi is formed on the surface of the layer by epitaxial growth of several μm.
A layer t'' of Pt with an impurity concentration lower than the surface concentration of the 21st layer is formed by epitaxial growth on the surface of the P"epi layer, and the N! A surge absorber section is formed on the same wafer by forming a P, + noise layer on a Pt layer opposite to the PT layer, electrically connecting this P, + layer and a cathode N2 layer formed on a Pt layer. It's a friend.

The resistance of the 21 layer is lowered by providing P"epi i with several μ door epitaxial growth on the surface of the 20-active Pt layer and the P+ layer.

A layer is provided to increase the Zener voltage.

G. Embodiment An embodiment of the present invention will be described below with reference to the drawings. The same parts as in FIG. 5 will be described with the same reference numerals.

In FIG. 1, gallium is first diffused into the original wafer N1 to form a P+ and Pt layer. At this time, the wafer N1 is 4 x 1013 CAtoms c
m-”) with a thickness of 400 μm, Pl, Pt
The surface concentration is 2×10 [AtomscWi], the depth is 30
Am Toshi next.

Next, make/expand the Pt layer? Form a metal layer N3. In this case, the surface concentration of the layer is 10” (Atoms Crn
-31T, diffusion depth 15μm. After forming the N1 layer,
Boron is diffused throughout the 27th layer to form a buried gate of the t layer. An oxide film 14 is formed on a portion of the surface of the P7 layer along the surface of the N1 layer and the P, N junction. This oxide film 1
P is applied to the surface of Pt layer and P+ layer without oxide film using 4゛.
2-layer is epitaxially grown, and a concentration of about 10'' (Atorns
cm-3] is grown to several μm. This P”epi layer has a base length growth surface concentration of 1015 (Atoms
cm-33) Epitaxially grow a single layer of Pt. The thickness of this P2-layer is 30 μm. In addition, P”epi
The layer provides the necessary sheet resistance for turn-off. With this configuration, the breaking ability can be improved and the Zener voltage can be determined based on the N5P2 junction cost.

On the P2- layer, ohmic layers p+, p, + and cathode layers N, , N, are formed. N,,N3 layer surface @degree is 4
X10 (Atom) and the depth is 8 μm. FIG. 2 is a net impurity concentration distribution diagram in the main GTO portion.

12 is an auxiliary electrode of the surge absorber section 13.

This auxiliary electrode 12 is connected to the cathode electrode 3.

FIG. 3A is an enlarged view of the main parts of the surge absorber section 16, and FIG. 3B is an equivalent circuit diagram of the surge absorber section 13, in which a high resistance R (shunt resistance) is connected in parallel. ing. The breakdown operation of the nine surge absorber parts 13 formed in this way has the characteristics as shown in FIG. In FIG. 4, the region of high differential resistance depends on the high resistance R, and the region of low differential resistance has N, P, and junction breakdown. The breakdown voltage at this time is about 70V as described above.

In other words, when the N1 layer is formed, only 70V-ffi is applied between the gate G and the cathode, and the gate G is damaged due to the surge generated at turn-off.

The junction to the cathode can be protected.

In the 7tGTO element formed as described above, N, P,
The Zener voltage is determined on the second side of the junction, but in this case, N
By increasing the diffusion depth of the six layers, the nine-way current resistance R shown in FIG. 3A increases. However, N of the GTO element,
Since the withstand voltage between A- and P, which is determined by the junction, decreases, the diffusion depth must be set to 9% by taking into account the withstand voltage between A- and P.

Narrow junction surface■ Part of the N, P junction surface is covered with a P2- layer of high resistance (approximately 5Ωα), so the second surface of the junction becomes a stable protective film, but the remaining part is covered with a 5iot'1 type protective film. To run away.

In the above embodiment, when there is no P+ap1 layer, P! 7tP lengthened on top of the layer! It is known that the Zener voltage is determined by the i-plane concentration of the N, P, junction +2) layer because it has a high resistance compared to the #ip layer. Here, to increase the Zener voltage, you can increase the resistance of the 21st layer, but if this is high, the P at the turn-off of the GTO element will decrease.
, the lateral resistance of the layer becomes high. As a result, GT
A friend who cannot increase the blocking ability of the O element.

However, in this embodiment, by providing Pepi/lt, it is possible to lower the total sheet resistance and increase the interrupting ability, and also to increase the Zener voltage.

Effects of H0 Invention As described above, according to this invention, the surge absorber part is formed on the same uniform bar, and several layers are formed on the surface of the Pt layer and the P+ layer (excluding a part of layer 21 covered with an oxide film). C) Since the P epi layer metallization is nine, it is possible to improve the blocking ability of the GTO element and also to increase the Zener voltage. Mayu.

In addition to the above, there is an advantage that external connection wiring for the surge absorber element is not required, and surges that enter through the wiring are eliminated. Furthermore, since no wiring is required, the possibility of short-circuiting or 1FrNA occurring in the wiring can be significantly reduced, and the case structure can be simplified. In addition, there are other excellent effects such as the elimination of external connecting parts, improved device reliability, and easier assembly.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a net impurity concentration distribution diagram of the main GTO section, and Figures 3A and B are enlarged views and equivalent circuits of the surge absorber section of Figure 1. figure,
Figure 4 shows the breakdown characteristics of the surge absorber, and Figure 5 shows the conventional example. The configuration diagram shown in FIG. 6 is an electrical circuit diagram of FIG. 5. 1... Main GTO section, 2... Amplification GTO section, 3...
Main GTO section cathode electrode, 4... Amplifying GTO section gate electrode, 5... Amplifying GTO section cut cathode electrode... Connection body, 7... Amplifying GTO section gate electric wire, 12... Surge absorber electrode , 16... surge absorber section, 14... oxide film, G... gate, K... cathode, A... anode, R... shunt resistor. 3----4GTO#7 saw 1-'Wk4----
IGTO Gun Gate Electric 1 Sales 5---416GTO#I5n-F Electric! 7------
12---One catch #71g on Masunobu GTO club gate electric shoulder! Extreme 14---Ikken A mouth hard

Claims (1)

[Claims] (1) Consisting of 4 layers, P_1N_1P_2N_2, P
By embedding P^+ low resistance layer in _2, P_1N_1
In a semiconductor device configured to control on/off the current flowing through P_2N_2, an independent N_5 layer is formed on the surface of the P_2 layer where the P^+ low resistance layer is formed, and the entire surface of this N_5 layer and the P_2 layer are formed.
An oxide film is formed across the N_5 junction to the surface of the P_2 layer, and this oxide film is left to form the P_2 layer and P_2 layer without an oxide film.
P^+ is formed by epitaxial growth of several μm on the surface of the ＿+ layer.
An epi layer is provided, and a P_2^- layer with an impurity concentration lower than the surface concentration of the P_2 layer is formed by epitaxial growth on the surface of this P^+epi, and a P_2^- layer with an impurity concentration lower than the surface concentration of the P_2 layer is formed on the surface of the N_5 layer.
A P_3^+ layer is formed on P_2^- at a position facing the N_2 layer across the region where the 2^- layer is not formed, and a cathode N_ is formed on this P_3^+ layer and P_2^- layer.
A gate turn-off thyristor characterized in that two layers are electrically connected and a surge absorber portion is formed on the same wafer.