JPS637494B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code error detection device, and more particularly to a code error detection device that detects that the number of out-of-synchronization pulses during a certain period of time is greater than or equal to a predetermined value.

In this type of conventional code error detection device,
The number of out-of-synchronization pulses during a certain period is counted, and if the count value is equal to or greater than a predetermined value at the end of the certain period, an error detection signal is output. That is, no error detection signal is issued until the end of a certain period of time, so that no appropriate action is taken, for example, for out-of-synchronization. However, when high reliability is required, for example an error rate of 10 ^-5 or less, the period required to detect this becomes long, and the certain period is set long. In particular, when the code transmission rate is slow, the certain period becomes even longer. For example, when the error pulses shown in FIG. 1a are counted by the monitoring clock pulses shown in FIG. 1b, the code error detection signal shown in FIG. 1c is output.

For this reason, conventional detection devices have the disadvantage that it takes a long time to output an error detection signal, which delays appropriate measures.

In view of the above-mentioned circumstances, the present invention aims to correct the conventional drawbacks, and its purpose is to provide a code error detection device that can quickly detect code errors.

In order to achieve this purpose, the code error detection device of the present invention constantly monitors the count value of a counter that counts error pulses within a certain period even during the period, and when the count value reaches a predetermined value, The monitor clock generator is configured to output a code error detection signal even if the code error detection signal is detected, and the monitor clock of the monitor clock generator that generates the timing clock for the predetermined period in response to the code error detection signal is stopped and the clock is restarted for a predetermined period of time. The present invention is characterized in that it includes a clock control section for generating pulses with a wide range of width.

Next, one embodiment of the present invention will be described in detail based on the drawings. FIG. 2 is a time chart showing an example of a monitoring clock pulse and a code error detection signal according to this embodiment. That is, when the number of out-of-synchronization pulses shown in d of the same figure reaches a predetermined value (5 in this example), a code error detection signal is output as shown in f of the same figure, and in response, the code error detection signal is output as shown in f of the same figure. As shown in Figure e, the monitoring clock pulse is temporarily stopped and a pulse of a certain length is generated again. In order to perform the above operations, a configuration as shown in FIG. 3 is used. That is, when an error pulse from the synchronization extraction protection circuit 1 is input, the counter 2 counts the number of error pulses and sends the counted number to the decoder 3 as a binary parallel output. Decoder 3
outputs a code error detection signal when a preset threshold number of pulses matches the output of the counter (FIG. 2f). The counter 2 counts the out-of-synchronization pulses during a period in which the supervisory clock pulse train of a certain period of time generated by the supervisory clock generator 4 is sent. After a certain period of clock pulses, the count value is cleared and the next period is counted. On the other hand, the code error detection signal from the decoder 3 is sent to the outside for appropriate processing and is also sent to the clock control section 5. In response to the code error detection signal, the clock control section 5 stops the clock pulses of the supervisory clock generation section 4, and then restarts generation of a clock pulse train at fixed time intervals. At this time, the counter 2 clears the count value and again counts the out-of-synchronization pulses during the next period. Therefore, when the number of error pulses reaches a predetermined number even during the fixed period, a code error detection signal is generated, and thereafter, the number of error pulses over the fixed period is monitored again. Instead of issuing an error detection signal after a certain period of time as in the conventional case, the detection signal can be issued quickly. Therefore, appropriate processing such as synchronization pull-in processing can be performed quickly.

FIG. 4 is a block diagram showing another embodiment of the present invention, in which a 4-bit counter 8 having the functions of the counter 2, decoder 3, and clock control section 5 of FIG. 3 is used. That is, the out-of-synchronization pulse is down-counted directly or via the decimal counter 6 and then sent to the 4-bit counter 8. Bit 3 of the binary parallel output of the 4-bit counter 8 is used as a code error detection signal (carry output) to simplify the decoder circuit. The supervisory clock is generated by cascading retriggerable one-shot multivibrators 9 and 10 for feedback. Then, the retriggerable one-shot multivibrator 9 is cleared by the code error detection signal of the 4-bit counter 8, and the generation of the monitoring clock pulse is returned to its initial state. The 4-bit counter 8 is cleared by a pulse at the terminal of the one-shot multivibrator 10, and counts the out-of-synchronization pulse of the next cycle. The code error detection signal is latched for a certain period of time by the retriggerable one-shot multivibrator 11 and sent to the outside. With the above configuration and operation, the same effects as the embodiment shown in FIG. 3 can be achieved.

As described above, the code error detection device of the present invention is configured to generate a code error detection signal as soon as the number of code errors reaches a predetermined number, and then again counts and monitors the number of errors during a certain period of time. Signals can be sent quickly.

[Brief explanation of the drawing]

FIG. 1 is a time chart showing an example of a conventional monitoring clock and code error detection signal, FIG. 2 is a time chart showing an example of a monitoring clock and code error detection signal according to an embodiment of the present invention, and FIG. 3 is a time chart showing an example of a conventional monitoring clock and code error detection signal. FIG. 4 is a block diagram showing one embodiment of the invention. FIG. 4 is a block diagram showing another embodiment of the invention. 7...Synchronization extraction protection circuit, 2...Counter, 3
...Decoder, 4...Monitoring clock generator, 5...
...Clock control section, 6... Decimal counter, 7...
Noah Gate, 8...4-bit counter, 9-11
...Retriggerable one-shot multivibrator.

Claims (1)

[Claims] 1. A monitoring clock generator that periodically generates pulses of a certain time width to determine the period for counting the number of error pulses output from the synchronization extraction protection circuit, and the number of error pulses in one period of the monitoring clock. and a decoder that detects that the count value of the counter is equal to or greater than a predetermined value and outputs a code error detection signal, the decoder has a is configured such that the count value of the counter is always inputted and a code error detection signal is output when the count value reaches a predetermined value,
The code error detection device further comprises a clock control section for stopping the monitoring clock and generating a pulse of a predetermined time width again in response to the code error detection signal.