JPS6374307A - Digital arithmetic circuit - Google Patents

Abstract

PURPOSE:To attain the clip processing in a simple way by adopting the constitution in which an input value is used as an output value when a carry output of the most significant bit of an adder is logical '1' from an output switch circuit and a prescribed value from a constant output circuit is used as the output value when logical '0'. CONSTITUTION:An input value 10 of 5-bit in natural binary notation is given to input lines 11-15 from an input terminal 1. A constant output value 30 from a constant output circuit 3 is given to a logical inverting circuit 7 through constant output lines 31-35 and the output inverted logically is given to an adder 4 as a logically inverted output value 70 through logical inverting output lines 71-75. The input value 10 and the logically inverted output value 70 are added by adders 4a-4e of the adder 4 and a carry output 49 from the most significant bit is outputted. Depending on the logic of the multiplexer, when the carry output 49 is logical '1', the input lines 11-15 are selected and when the carry output 49 is logical '0', the constant output lines 31-35 are selected and the result is outputted to an output terminal 9 through output lines 61-65. Thus, the clip processing is attained by using adders and a very small number of control circuits without increasing number of components of a digital arithmetic circuit applying clip processing.

Description

Detailed Description of the Invention Field of the Invention The present invention relates to a nonlinear arithmetic circuit in digital signal processing, and provides a digital arithmetic circuit having a characteristic of clipping relatively low-level amplitude components of a digital signal. This is what I am trying to do.

Conventional technology In recent years, with the advancement of digital technology, logic elements, memory elements, etc. have become more integrated and faster, and as a result, digital signal processing methods are increasingly being introduced in place of conventional analog signal processing methods. . In digital signal processing techniques, signals are treated as numerical values expressed in binary, and these numerical values are processed by performing various operations. One example of such digital signal processing is nonlinear operation. This nonlinear processing is literally performed by nonlinear calculations, but nonlinear calculations are generally more complex than addition calculations, etc. whose calculation algorithms are linear calculations. For this reason, a simple method is to use ROM (read-only memory).
Conventionally, a method called an arithmetic table reference method using a sequential read-only memory has been used. In the calculation table reference method using ROM, the desired nonlinear characteristics are determined in advance by R.
The input value is stored in the OM, and when the input value is given to the ROM, an output value corresponding to the nonlinear characteristic is output.

One of the nonlinear processes using the above method is a clip that uses a predetermined minimum value as the output value when the input value is within a predetermined value range, and uses the input value as the output value when the input value is outside the predetermined value range. There is processing.

This clip processing is used to remove minute amplitude noise superimposed on digital signals, etc. In particular, by using the calculation table reference method mentioned above, it is possible to perform flexible processing such as arbitrarily changing desired characteristics, and analog signal processing has a big advantage over.

An example of a digital arithmetic circuit that performs clip processing using the conventional arithmetic table reference method described above will be described below with reference to the drawings.

FIG. 7 is a block diagram showing the configuration of a digital arithmetic circuit that performs clip processing using a conventional arithmetic table reference method, and FIG. 8 is a block diagram showing a specific example. In addition, Fig. 2 shows an example of the input/output characteristics of clip processing, with a solid line (
1) is the input/output characteristic. In FIG. 7, 1 is an input terminal for inputting an input value, 9 is an output terminal for outputting an output value subjected to clip processing, and 2 is a clip processing circuit that performs clip processing using a conventional arithmetic table reference method. In FIG. 8, the same numbers as in FIG. 7 correspond to each other, and 2a is a ROM that stores output values as data shown in FIG. 2 at each address corresponding to an input value, and 2b is the address terminal of ROM2a, 2C
is a data output terminal of the ROM.

The operation of the digital arithmetic circuit that performs clip processing using the arithmetic table reference method configured as described above will be described below. Input terminal 1 and output terminal 9
are respectively located in ROM2a. In addition, the ROM 2a stores output values as data as shown by the solid line (11) in FIG. 2 at each address corresponding to the input value from input terminal 1. Then, the address of the ROM 2a corresponding to the input value is selected. Since the output value as shown in the solid line (1) in FIG. When the input value is within the predetermined range (from "0" to "k" in Figure 2), the predetermined minimum value is set; ), the input value can be obtained as the output value, thereby realizing clipping processing. (Reference: Murakami, Enami: Color corrector, Journal of the Society of Television Engineers, 33.4 (1979) P291-295)
Problems to be Solved by the Invention However, in the above configuration, since a ROM is used, the capacity of the ROM increases as the number of bits of the input value increases (increase the number of input bits by n bits). However, if you try to introduce the above configuration into an LSI (large scale integrated circuit) for digital signal processing, the scale of the LSI will become very large. It had some problems.

In view of the above problems, the present invention provides a digital arithmetic circuit without increasing the number of elements constituting the digital arithmetic circuit, and in which an increase in the number of bits of an input value does not significantly affect the increase in the number of elements. It is.

Means for Solving the Problems In order to solve the above problems, the digital arithmetic circuit of the present invention has a natural 2
a constant output circuit that inputs an input value in decimal representation and outputs a predetermined value in N-bit natural binary representation; and inputs the output of the constant output circuit, and outputs the output after logically inverting the output of the constant output circuit. a logic inversion circuit, an adder that adds the input value and the output of the logic inversion circuit and outputs a carry from the most significant bit of the addition result, and the carry from the most significant bit of the adder has a logic value of "1"; ”, the input value is used as the output value, and when the carry from the most significant bit of the adder is a logical value “0”, the output value is the output value of the constant output circuit. It is something that

According to the above-described configuration, the present invention first uses an adder, a constant output circuit, and a logic inversion circuit to perform rip processing on an input value and a predetermined value (as shown by the solid line (1) in FIG. 2), the predetermined value is " If the input value is outside the predetermined range for clipping (more than "k" in Figure 2),
In this case, the carry output from the most significant bit of the adder is the logical value '1'', and if the input value is within the predetermined range for clipping (from 0'' to 'k' in Figure 2), the carry output from the most significant bit of the adder is Utilizing the fact that the carry output from the adder is a logical value "0", when the carry output of the most significant bit of the adder is a logical value "1", the input value is set as the output value by the output switch circuit, and the logical value "1" is set as the input value. In the case of "0", a predetermined value from the constant output circuit is used as the output value, thereby realizing the characteristic of performing the desired clipping process using an adder and a small number of control circuits.

Embodiment Hereinafter, an embodiment of the digital arithmetic circuit of the present invention will be described.
This will be explained using drawings.

FIG. 1 is a block diagram showing the configuration of a digital arithmetic circuit that performs clip processing according to the present invention. In FIG. 1, 1 is an input terminal to which an input value 10 in natural binary representation of N bits (N is any integer greater than or equal to 0) is input. 3 is a constant output circuit, which has an N-bit natural binary representation constant "k" as a constant output value 30. Here, the N-bit natural binary representation means that a positive integer X from zero to 2N-1 is expressed as an N-bit code x1 (
i=1-N), code string (xl+x2°X...
..., xN) and express it as a -. Also, hereafter x1 is called the most significant bit) and XN is called the least significant bit. For example, 5 is the code string (
00011).

7 is a logic inversion circuit which takes the logic inversion of the constant output value 30 from the constant output circuit 3 and outputs a logic inversion output value 70; That is, if the constant output value 30 is expressed as a code string (00011), the logically inverted output value 70 is expressed as a code string (11100).

4 is an adder which adds the input value 10 and the logically inverted output value 70, and outputs a carry output 49 from the most significant bit. Here, the carry output from the most significant bit means a carry from the Nth bit to the (N+1)th bit.

In other words, for example, a positive integer expressed as a 5-beat natural binary number.
A code string (00011) expressing 3” and a code string (11
111), the carry output from the most significant bit becomes a logical value "1" because a carry occurs from the 5th bit of the code string.

6 is an output switch circuit, which has a carry output 49 from the adder 4, an input value 10, and a constant output value 30J, one input power 76
-Sui 1. 63 From the above, when the carry output 49 from the adder 4 is a logical value "1", the input value 10 is set as the output value 6o of the output inch circuit 6, and when the carry output 49 from the adder 4 is a logical value "0", it is set as the constant output value. 3o is taken as the output value 60 of the output inch circuit 6. Reference numeral 9 denotes an output terminal which outputs an output value 6o that has been subjected to clip processing.

The operation of the digital arithmetic circuit configured as described above for performing crib processing will be described below with reference to FIGS. 1 and 2.

First, FIG. 2 shows the input/output characteristics of the digital arithmetic circuit that performs the clipping process of the present invention, and the solid line (indicated by 11) shows the added value of the adder 4 and the dotted line (2). This is the input/output characteristic with the input value 10. The solid line (3) is the input/output characteristic between the carry output 49 from the adder 4 and the input value 10. When the input value 10 is "k" or less, the carry output 49 is logic. The carry output 49 has a logic value of "13" when the value is "0" and the value is "k+l" or more.

Here, when an input value 10 is given to the input terminal 1, the adder 4 adds a logically inverted output value 70 of the input value 10 and the constant output value 30, and the added result is carried to the carry output 49.
is output as In FIG. 2, the dotted line (2) indicates the added value. Here, in Fig. 2, when the input value 10 is less than °k'', the carry output 49 has the logical value ``0''.
When the input value 10 is +1° or more, the carry output 49 has a logic value "L", that is, when the carry output 49 has a logic value "O", the output value 60 is set to °k.
”, and when the carry output 49 has the logical value “1”, the input value 10 is set to the output value 60, so that the solid line (
Desired input/output characteristics as shown in 1) can be obtained. This process is performed by the output cusp inch circuit 6, which will be described next.

The output inch circuit 6 inputs the carry output 49, the input value 10, and the constant output value 30 from the adder 4, and switches the switch 65.
Therefore, when the carry output 49 has a logical value "1", the input value 10 is selected, and when the carry output 49 has the logical value "O", the constant output value 30 is selected, and this selected value is It is output as an output value 60. That is, this output value 6
0 means that the input value 10 is "1" in the range from "02 to k", and the input value is 10 above "k+l".As a result, the input/output characteristics of the input value 10 and the output value 60 are as shown in Figure 2. solid line(
1).

The constant output circuit 3 uses a register, the logic inversion circuit 7 uses an inverter, and the switch 6 of the output switch circuit 6
5 can be realized by a multiplexer, and adder 4 can be realized by an adder.

As described above, according to this embodiment, the adder 4, the constant output circuit 3, and the logic inversion circuit 7 generate N pins (N is 0
The input value 10 of the natural binary representation of (any integer above) and N
By adding the logical inverted output value 70 of the constant output value 30, which is the natural binary representation of the bit, the carry output 49 from the adder 4 becomes a logical value ``0'' in the predetermined range in which the clipping process is performed. Taking advantage of this fact, when the carry output 49 has the logical value "■", the output switch circuit 6 sets the input value 10 to the output value 60, and the carry output 49
When is the logical value “O”, the constant output 4a30 becomes “ko”.
Assuming that the output is 1lr60, a digital arithmetic circuit having input/output characteristics for performing rip processing as shown in 1-L7, 1-L7, 1-L7, Figure 1 and 1t1) is realized using an adder and a small number of control circuits.

FIG. 3 is a block diagram showing a specific example of a digital arithmetic circuit that performs clip processing according to the present invention.

In order to make the explanation easier to understand, input values 10. The number of bits of constant output value 30 and output value 60 is set to 5.
bit, and set the range for clip processing from "0" to "3".
Let me explain by giving an example. In FIG. 3, the same numbers as in FIG. 1 correspond to each other. 1st
The input lines 11 to 1 in Fig. 3 correspond to the input value 10 in the figure.
5, 11 is the most significant bit, 15 is the least significant via), and input lines 11 to 1.5 input the 5-bit input value 10.
It represents. Similarly, constant output value 30 is constant output line 3
1-35. The logic inversion output value 70 is the logic inversion output line 71~
75. Output value 60 is represented by output lines 61-65. 4a to 4e are addition elements (hereinafter referred to as adders) constituting an adder, and have input terminals a and b that input two input values to be added, and a carry input terminal C0 that inputs a carry from the lower bit. and a carry output terminal C8 that outputs a carry to the lower bit, and an output terminal S that outputs the addition result, and 6a to 6e are multiplexers, which have three input terminals a, b, and s and one Inverters 7a to 7e are provided with an input terminal I and an output terminal 0, and their input/output logic is shown in FIG.

A specific example of the digital arithmetic circuit configured as described above that performs clip processing will be described.

First, input value 1 of 5-bit natural binary representation from input terminal 1.
0 is input via input lines 11-15.

Constant output value 30 from constant output circuit 3 is connected to constant output line 31
~35 is input to the logic inversion circuit 7, and the logically inverted output is output as the logic inversion output value 70 to the logic inversion output line 71~
75 outputs it to the adder 4. The input value 10 and the logically inverted output value 70 are added by the adders 4a to 4e of the adder 4, and a carry output 49 is output from the most significant bit. In this specific example, the range for clip processing is from “0” to 3.
” From the example given above, the constant output value 30
The numerical value "k" expressed by is "3", and the constant output line 31
~35 is expressed as (00011). For example, if the input value lO is 2, the input lines 11 to 15 are (00
010), and the added value of adder 4 is (11110
) and the carry output 49 becomes "θ". Similarly, the additional value for input value 10 from 0" to 31" is:
In FIG. 2, the dotted line (2) represents k''-3'', and the carry output 49 represents the solid line (3). The carry output is output to the output switch circuit 6, and the multiplexer 6
Connected to select terminals S of a to 6e. The logic of the multiplexer as shown in FIG.
When the carry output 49 is "1", the input lines 41 to 45 are selected, and when the carry output 49 is "0", the constant output lines 31 to 35 are selected.
is selected and output to the output terminal 9 through the output lines 61 to 65.

With the above operation, in this specific example, "k"-
3'', and input/output characteristics for performing rip processing can be obtained.

FIG. 5 shows the input value 10. Carry output 49. The comparison between the added value and the output value 60 is specifically shown. In this specific example, the number of input/output bits is 5 bits, and the range for clipping is O''~''3''.
However, this is an example to make the explanation easier to understand. Adders, multiplexers, and inverters can be increased or decreased depending on the number of input/output bits. Also, the range for clipping can be determined by applying the desired value to the constant output circuit 3. Just set it.

FIG. 4 is a block diagram showing another specific example of a digital arithmetic circuit that performs clip processing according to the present invention.

In this figure, the same numbers as in FIG. 3 correspond to each other. Further, the number of input/output bits for performing clip processing and the characteristics of clip processing are completely the same as in the previous specific example. What differs from the configuration in FIG. 3 are the adders 4c and 4d in FIG.

This is the point where the input line 13 is connected to the carry input terminal CI of the adder 4b.

Another specific example of the digital arithmetic circuit configured as described above that performs clip processing will be described.

When paying attention to the adder 4e of the adder 4 in FIG.
Since the inputs C and C of the adder 4e always have a logical value of "0", the output C8 of the adder 4e also always has a logical value of "O". Similarly, the output c0 of the adders e and d always has a logical value of "0". ”.For the adder 4c, the input line C1 is always the logical value “1” and the human power C1 is always the logical value “0”, so if the input line 13 is the logical value “1”, the adder 4
The output C6 of the adder 4C has a logic value "1", and when the input line 13 has a logic value "O", the output C0 of the adder 4C has a logic value 30'.
becomes. For the above reasons, 7 of adder 4 in FIG.
The adders 4c, 4d, and 4e can be deleted, and a logic configuration equivalent to that shown in FIG. 3 can also be obtained by connecting the input line 13 to the input C1 of the adder 4b. Figure 4 shows how this has been achieved.

The reason is that the constant output value 30 from the constant output circuit 3 is
”, that is, the constant output lines 31 to 35 are expressed as (00011), but in general, when the logical value “1” continues from the lowest bit to the upper bit of the constant output line that realizes the constant output value 30. Similarly, the adder of adder 4 can be deleted.For example, if L logical values "1" continue from the lowest bit to the upper bit of the constant output line, (L+1)
Adders corresponding to (L+2) from the least significant bit can be deleted from the input C1 of the adder corresponding to (L+2) from the least significant bit.
1) Desired characteristics can be obtained by connecting the second input line.

In other words, if the input value is N bits and M=N-L, the input line inputs only M bits from the higher bits,
Desired characteristics can be obtained by connecting the Mth bit from the upper bit of the input line to the carry input terminal of the (M-1)th bit from the upper bit of the adder.

By adopting the configuration shown in the specific example of FIG. 4 in this manner, the number of adders in the adder 4 can be reduced, making it possible to further reduce the circuit scale.

Effects of the Invention As described above, the present invention adds an input value and a logic inversion output of a predetermined value using an adder, a constant output circuit, and a logic inversion circuit, and when the input value is outside a predetermined range in which clipping processing is performed, the adder The carry output from the most significant bit of the adder is a logical value "1", and the carry output from the most significant bit of the adder is a logical value "0" when the input value is within a predetermined range for clipping. When the carry output of the most significant bit of the adder is a logical value "1", the input value is set as the output value, and when the carry output of the most significant bit of the adder is a logical value "O", the predetermined value from the constant output circuit is set as the output value. Since the output value is configured to be used as an output value, there is no need to increase the number of elements that make up the digital arithmetic circuit that performs clip processing, and an increase in the number of bits of the input value does not have a large effect on the increase in the number of elements. , an excellent effect can be obtained in that a digital arithmetic circuit that performs clip processing can be realized using an adder and a small number of control circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital arithmetic circuit according to an embodiment of the present invention, FIG. 2 is an input/output characteristic diagram showing the input/output characteristics of the digital arithmetic circuit of the present invention, and FIG. 4 is a block diagram of a digital arithmetic circuit in another example of the present invention, FIG. 5 is an input/output characteristic diagram comparing input and output values of a specific example of the present invention, and FIG. 3 and 4 are logic diagrams showing the logic of each logic element, FIG. 7 is a block diagram showing the configuration of a conventional digital arithmetic circuit, and FIG. 8 is a block diagram showing a specific example of FIG. 7. 1...Input terminal, 9...Output terminal, 3
...Constant output circuit, 4...Adder, 7
...Logic inversion circuit, 6 ... Output switch circuit, 2 ... Conventional digital arithmetic circuit. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1: 4':? Figure 2 Figure 5 Graduation value (000//) Figure 6 Figure 7 Figure 8

Claims (3)

[Claims] (1) A constant output circuit that receives an input value in natural binary representation of N bits (N is any integer greater than or equal to 0) and outputs a predetermined value in natural binary representation of N bits; a logic inversion circuit that inputs an output, logically inverts the output of the constant output circuit and outputs it; and an addition that adds the input value and the output of the logic inversion circuit and outputs a carry from the most significant bit of the addition result. When the carry from the most significant bit of the adder is a logical value "1", the input value is the output value, and when the carry from the most significant bit of the adder is a logical value "0", the input value is the output value. A digital arithmetic circuit comprising an output switch circuit whose output value is the output of the constant output circuit. (2) The adder has an input terminal that inputs at least two input values to be added, a carry input terminal that inputs the carry from the lower bit, and a carry output terminal that outputs the carry to the upper bit. The carry input terminal of the addition element is connected to the carry output terminal of the lower bit for each bit, and the carry input terminal of the addition element of the lowest bit has a logic value "0". ” is connected, and the carry output terminal of the adder element of the most significant bit outputs to the output switch circuit as a carry from the most significant bit of the adder. The digital arithmetic circuit described in Section 1. (3) The adder inputs M bits from the upper bits of the input value (M is an integer greater than or equal to 0 and less than or equal to N), and the M-th bit from the upper bits of the input value is input from the upper bits of the addition element. The digital arithmetic circuit according to claim 1, wherein the digital arithmetic circuit is connected to the carry input terminal of the (M-1)th bit.