JPS6373535A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6373535A
JPS6373535A JP21838086A JP21838086A JPS6373535A JP S6373535 A JPS6373535 A JP S6373535A JP 21838086 A JP21838086 A JP 21838086A JP 21838086 A JP21838086 A JP 21838086A JP S6373535 A JPS6373535 A JP S6373535A
Authority
JP
Japan
Prior art keywords
metal film
film pattern
unit element
pattern
marking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21838086A
Other languages
Japanese (ja)
Other versions
JPH0516664B2 (en
Inventor
Hideo Ishikawa
石川 英郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21838086A priority Critical patent/JPS6373535A/en
Publication of JPS6373535A publication Critical patent/JPS6373535A/en
Publication of JPH0516664B2 publication Critical patent/JPH0516664B2/ja
Granted legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To make it possible to carve a marking trace having a specified dimension even with a laser marker equipment of small power capacity, and achieve the stable optical reading of a defective unit element region, by providing each of the unit element region on a wafer with a metal film pattern for wiring and a silicon oxide film in the manner in which they are locally mixed and concentrated in every small area unit. CONSTITUTION:On a silicon oxide film 2 as an insulating film, a metal film pattern 3 for wiring is formed in the manner in which the metal film pattern 3 and the silicon oxide film 2 are locally concentrated in every small area unit and mixed so as to constitute a slit shape. In the case of such a structure, when the metal film pattern 3 in a defective unit element region is irradiated by a laser ray, its power is converted to heat on each metal film pattern 3 on a pellet surface. As the pattern width is narrow, the heat is not easily dissipated into the peripheral part but makes the oxide film 2 in the vicinity of each metal film pattern 3 melt together to form a marking trace 4. In a selecting process, an optical checking equipment discriminates the marking trace 4 and determines a defective.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にし゛−ザー
マー力装置を用いた半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device using a thermal power device.

〔従来の技術〕[Conventional technology]

従来、ICの組立工程においては良品ペレットのみを用
いるため、事前に不良品ペレットの除去を行っている。
Conventionally, since only good pellets are used in the IC assembly process, defective pellets are removed in advance.

この不良品ペレットに対する除去は、ペレットに切離す
前のウェーハ状態において、半導体素子を集積して一機
能を達成しかつスクライブ線で囲まれる各単位素子領域
(以下単に単位素子領域と称す)のパターンにレーザー
マーキングを行い、それを光学的手段により選別し除去
しているが、レーザーマーキングする際に前記単位素子
領域表面のどのパターン及びどこの領域に打刻するかに
ついては、特に定っなものはなく、品種毎に適当な位置
に小さなマーキングをしていた。
The defective pellets are removed by forming a pattern of each unit element area (hereinafter simply referred to as unit element area) that integrates semiconductor elements to achieve one function and is surrounded by scribe lines in the wafer state before being separated into pellets. Laser marking is performed on the surface of the unit element, and then it is sorted and removed by optical means. However, there are no particular rules regarding which pattern and which area on the surface of the unit element area to be engraved when laser marking is performed. Instead, small markings were placed at appropriate locations for each variety.

例えば、電源ライン等の配線幅の太いパターンにマーキ
ングをしたり、または信号ライン等の配線幅の細いパタ
ーンにマーキングをしている。
For example, markings are made on patterns with wide wiring widths such as power supply lines, or markings are made on patterns with narrow wiring widths such as signal lines.

前者の配線幅の太いパターンにマーキングする場合は、
金属材料の熱伝導率が大きいため、レーザー光線のエネ
ルギーが熱に変換されても周辺に放散されてしまい、マ
ーキング跡は小さいものとなってしまう。
When marking the former pattern with a thick wiring width,
Since the thermal conductivity of metal materials is high, even if the energy of the laser beam is converted into heat, it is dissipated into the surrounding area, resulting in a small marking mark.

また後者の配線幅の小さいパターンにマーキングする場
合については、第2図(a)、(b)を参照して説明す
る。
The latter case of marking a pattern with a small wiring width will be explained with reference to FIGS. 2(a) and 2(b).

第2図(a>、(b)はそれぞれ単位素子領域の部分平
面図およびY−Y’線断面図である。
FIGS. 2(a) and 2(b) are a partial plan view and a sectional view taken along the line Y-Y' of the unit element region, respectively.

半導体基板11上に厚さがほぼ1μmのシリコン酸化W
A12を形成し、その上に信号ラインとなる厚さがほぼ
2μmの金属層パターン13を形成している。ここで、
前記単位素子領域が不良品と判定されたときは、レーザ
ーマーカー装置(図示省略)からレーザー光線を照射し
マーキング跡14をつけパターン13を破断する。実際
の半導体基板11に対するレーザー光線の照射面積は点
線で示す直径が200μm程度の照射領域15になるが
、シリコン酸化膜12は透明のためレーザー光線は透過
してしまう。
Silicon oxide W with a thickness of approximately 1 μm is deposited on the semiconductor substrate 11.
A12 is formed, and a metal layer pattern 13 having a thickness of about 2 μm and serving as a signal line is formed thereon. here,
When the unit element region is determined to be a defective product, a laser beam is irradiated from a laser marker device (not shown) to leave a marking mark 14 and break the pattern 13. The actual irradiation area of the semiconductor substrate 11 with the laser beam is an irradiation area 15 with a diameter of about 200 μm as shown by the dotted line, but since the silicon oxide film 12 is transparent, the laser beam passes through it.

要するに、マーキング跡14以外に照射されるレーザー
光線はその下の半導体基板11に吸収されマーキング跡
14は小さくなる。従って、通常のエネルギーのレーザ
ー光線でマーキングする場合は、信号ラインが適当に密
集している領域を品種毎に選択してマーキングしていた
In short, the laser beam irradiated onto areas other than the marking trace 14 is absorbed by the semiconductor substrate 11 below, and the marking trace 14 becomes smaller. Therefore, when marking with a laser beam of normal energy, an area where signal lines are appropriately concentrated is selected and marked for each product type.

次に、上述のマーキングされている不良の単位素子領域
を除去するときは、光学的にマーキング跡を検出する方
法が採用されはじめているが、現在の段階では不良な単
位素子領域の全面を識別するだけの能力はなく限られた
小領域についてのみマーキングの有無の判定が行われて
いるにすぎない。
Next, when removing the marked defective unit element area mentioned above, a method of optically detecting the marking trace is beginning to be adopted, but at the current stage, the entire surface of the defective unit element area is identified. However, the presence or absence of markings is only determined in a limited small area.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の不良な単位素子領域の除去のためのマー
キングは、パターンの熱伝導率やシリコン酸化膜の光透
過性の技術的問題があり、パターンの大小いづれの場合
もマーキング跡は少さくなり、光学的にマーキング跡を
検出するとき不確実になるという欠点がある。
The above-mentioned conventional marking for removing defective unit element regions has technical problems with the thermal conductivity of the pattern and the light transmittance of the silicon oxide film. However, there is a drawback that there is uncertainty when optically detecting marking traces.

特に、拡散用のパターンを共通に設は配線用のパターン
のみを異ならせるマスタースライス方式の集積回路にお
いては、全品種についてレーザーマーキングする位置を
同一にすることが望ましい、しかしながら、現在の集積
回路の配線構造は品種によって異なり、マーキング位置
を固定した場合には品種によりそこに電源ラインがあっ
たり絶縁膜だけであったりする。この様な場合には、前
述のとおりマーキングの大きさは小さく不安定になり、
通常のパワーのレーザーマーカー装置ではマーキングが
不可能になるという欠点がある。
In particular, in master slice integrated circuits where the diffusion pattern is common and only the wiring pattern is different, it is desirable to make the laser marking position the same for all products. The wiring structure differs depending on the product type, and if the marking position is fixed, depending on the product type, there may be a power line there or there may be only an insulating film. In such a case, as mentioned above, the size of the marking becomes small and unstable,
The drawback is that marking is impossible with a laser marker device of normal power.

本発明の目的は、従来のかかる不良な単位素子領域にマ
ーキングを施しそれを良品と区別し除去するにあたり、
通常のパワーのレーザーマーカー装置を用いてもマーキ
ングの大きさを大きくでき確実に不良な単位素子領域の
除去を行う半導体装置の製造方法を提供することにある
The purpose of the present invention is to perform the conventional marking on defective unit element regions to distinguish them from good products and to remove them.
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can increase the size of marking even when using a laser marker device of normal power, and can reliably remove defective unit element regions.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、半導体素子を集積し
て一機能を達成しかつスクライブ線で囲まれる単位素子
領域を複数個有する半導体基板上に絶縁膜を被覆する工
程と、前記絶縁膜上に配線用の金属膜パターンと前記絶
縁膜とが小面積単位で局部的に混在し集中して形成する
工程と、不良の前記単位素子領域の場合のみ前記金属膜
パターン上にレーザーマーカー装置からのレーザー光線
を照射しマーキングする工程と、前記マーキングした跡
を光学的に識別し不良品として選別する工程とを含んで
構成される。
A method for manufacturing a semiconductor device according to the present invention includes the steps of: coating an insulating film on a semiconductor substrate having a plurality of unit element regions surrounded by scribe lines and integrating semiconductor elements to achieve one function; A process of forming a metal film pattern for wiring and the insulating film in a locally mixed and concentrated manner in small area units; The method includes a step of marking by irradiating a laser beam, and a step of optically identifying the marking trace and selecting it as a defective product.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)、(b)は本発明の一実施例を説明するた
めの不良な単位素子領域の一部の平面図およびx−x’
線断面図である。
FIGS. 1(a) and 1(b) are a plan view of a part of a defective unit element region and x-x' for explaining one embodiment of the present invention.
FIG.

第1図(a)、(b)において、半導体基板1の上に絶
縁膜としてシリコン酸化!2を形成することは従来と同
じであるが、本実施例においてはこのシリコン酸化膜2
上に配線に使用する金属膜パターン3を小面積単位で局
部的に集中し金属膜パターン3とシリコン酸化膜2とが
混在してスリット状になるように形成する。
In FIGS. 1(a) and 1(b), silicon oxide is formed as an insulating film on a semiconductor substrate 1! 2 is the same as the conventional method, but in this embodiment, this silicon oxide film 2
A metal film pattern 3 used for wiring is locally concentrated in small area units on top, and the metal film pattern 3 and silicon oxide film 2 are formed in a slit-like manner.

この様な構造にすると、不良な単位素子領域の金属膜パ
ターン3にレーザー光線を照射したときそのパワーはペ
レット表面の各金属膜パターン3上で熱に変換される。
With such a structure, when the metal film pattern 3 in the defective unit element region is irradiated with a laser beam, the power is converted into heat on each metal film pattern 3 on the pellet surface.

その熱はパターンの幅が狭いため容易には周囲に放散さ
れずに各金属膜パターン3の近傍のシリコン酸化膜2を
一緒に溶融しマーキング跡4をつくる。
Since the width of the pattern is narrow, the heat is not easily dissipated to the surroundings, and melts the silicon oxide film 2 in the vicinity of each metal film pattern 3, thereby creating a marking mark 4.

次に、選別工程において光学的判定装置(図示省略)に
より単位素子領域のマーキング跡4を識別し不良品と判
定する。
Next, in a sorting process, an optical determination device (not shown) identifies the marking traces 4 in the unit element area and determines the product to be defective.

このように、不良な単位素子領域に大きなマーキング跡
4が設けられると、選別工程において通常の光学的判定
装置により容易に識別し不良品と判定できるので、切離
された不良な単位素子領域を良品扱いしてしまうことも
解消される。
In this way, if a large marking trace 4 is provided on a defective unit element region, it can be easily identified and determined as a defective product by a normal optical judgment device in the sorting process, so that the separated defective unit element region can be easily identified and judged as a defective product. This also eliminates the problem of treating products as non-defective products.

なお、上記実施例において説明した金属膜パターンを配
線用金属膜パターンとして説明したが、集積回路の信号
線と兼用であってもよい。
In addition, although the metal film pattern explained in the said Example was demonstrated as the metal film pattern for wiring, it may also be used as the signal line of an integrated circuit.

また金属膜パターンは線状だけでなく点状に散在させて
もよい。
Further, the metal film pattern may be scattered not only in a linear pattern but also in a dotted pattern.

要するに、レーザ光線の照射面積に比べ、金属膜パター
ンとシリコン酸化膜とが小面積単位で局部的に混在して
集中していればよい。
In short, it is sufficient that the metal film pattern and the silicon oxide film are locally mixed and concentrated in small area units compared to the area irradiated with the laser beam.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はウェーハ上の各単位素子
領域に配線用金属膜パタ゛−ンとシリコン酸化膜とが小
面積単位で局部的に混在して集中するように設けること
により、小容量パワーのレーザーマーカー装置でも一定
した大きさのマーキング跡を打刻でき、不良な単位素子
領域に対する安定した光学的読取りを達成できる半導体
装置の製造方法を得られる効果がある。
As explained above, the present invention provides a small capacitance by providing a wiring metal film pattern and a silicon oxide film locally mixed and concentrated in small area units in each unit element region on a wafer. Even with a laser marker device of high power, a marking trace of a constant size can be engraved, and there is an effect that a method of manufacturing a semiconductor device can be obtained that can achieve stable optical reading of a defective unit element region.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)は本発明の一実施例を説明するた
めの不良な単位素子領域の一部の平面図およびx−x’
線断面図、第2図(a)、(b)は従来の不良な単位素
子領域の一部の平面図およびY−Y’線断面図である。 1・・・半導体基板、2・・・シリコン酸化膜、3・・
・金属膜パターン、4・・・マーキング跡。 34ト眉−1A更ハ0ター、ン 第 1 図
FIGS. 1(a) and 1(b) are a plan view of a part of a defective unit element region and x-x' for explaining one embodiment of the present invention.
2(a) and 2(b) are a plan view and a sectional view taken along YY' line of a part of a conventional defective unit element region. 1... Semiconductor substrate, 2... Silicon oxide film, 3...
・Metal film pattern, 4...marking traces. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を集積して一機能を達成しかつスクライブ線
で囲まれる単位素子領域を複数個有する半導体基板上に
絶縁膜を被覆する工程と、前記絶縁膜上に配線用の金属
膜パターンと前記絶縁膜とが小面積単位で局部的に混在
し集中して形成する工程と、不良の前記単位素子領域の
場合のみ前記金属膜パターン上にレーザーマーカー装置
からのレーザー光線を照射しマーキングする工程と、前
記マーキングした跡を光学的に識別し不良品として選別
する工程とを含むことを特徴とする半導体装置の製造方
法。
A step of coating an insulating film on a semiconductor substrate having a plurality of unit element regions surrounded by scribe lines and integrating semiconductor elements to achieve one function, and forming a metal film pattern for wiring on the insulating film and the insulating film. a step of forming the metal film pattern locally mixed and concentrated in small area units; a step of irradiating and marking the metal film pattern with a laser beam from a laser marker device only in the case of the defective unit element region; A method for manufacturing a semiconductor device, comprising the step of optically identifying marking marks and selecting them as defective products.
JP21838086A 1986-09-16 1986-09-16 Manufacture of semiconductor device Granted JPS6373535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21838086A JPS6373535A (en) 1986-09-16 1986-09-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21838086A JPS6373535A (en) 1986-09-16 1986-09-16 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6373535A true JPS6373535A (en) 1988-04-04
JPH0516664B2 JPH0516664B2 (en) 1993-03-05

Family

ID=16718990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21838086A Granted JPS6373535A (en) 1986-09-16 1986-09-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6373535A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227919A (en) * 1994-12-09 1996-09-03 Sgs Thomson Microelectron Sa Marking method for integrated circuit using laser and equipment therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227919A (en) * 1994-12-09 1996-09-03 Sgs Thomson Microelectron Sa Marking method for integrated circuit using laser and equipment therefor
US6559409B1 (en) * 1994-12-09 2003-05-06 Sgs-Thomson Microelectronics S.A. Method for marking integrated circuits with a laser

Also Published As

Publication number Publication date
JPH0516664B2 (en) 1993-03-05

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