JPS6371000A - Track holding circuit - Google Patents

Abstract

PURPOSE:To get the complete suite of the characteristics of two holding parts, and to constitute a track holding circuit with high accuracy by providing two sets of the track holding circuit and switching them alternately. CONSTITUTION:Sample switches sw1 and sw2 come to ON or OFF alternately. Now, when the sw2 is assumed to be ON and the sw1 to be OFF, a capacitor C2 changes moment by moment according to a signal level from an input stage amplifier 1, and the capacitor voltage is taken out through a buffer amplifier 3 and an output change over switch sw3, and the taken out signal corresponds to the change of the signal of the input stage amplifier 1 and comes to be a track output ST. On the other hand, in the capacitor C1, the voltage at the time just after the sample switch sw1 comes to OFF, is held. The voltage is taken out through the buffer amplifier 2 and the sw4, and the taken out signal is the voltage at the time just after the sample switch sw1 comes to OFF, and comes to be a holding output SH. Namely, the track output ST and the SH are taken out.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Object of the Invention [Field of Industrial Application] The present invention relates to speeding up a track and hold circuit.

(Prior Art) A track and hold circuit (hereinafter referred to as T-8 circuit) is a circuit that has a function of passing an introduced analog input signal V according to a control signal and holding it. Used in the input stage of conversion circuits (analog/digital conversion circuits), etc.

This T-)-1 circuit charges a hold capacitor according to the level of an analog input signal during tracking and outputs a signal according to the analog input signal to the next stage. Furthermore, during hold, it operates to output a signal to the next stage based on the voltage charged in the capacitor at the start of hold.

[Problem that the invention seeks to solve]

In this way, the T-8 circuit charges the hold capacitor during tracking. Therefore, when the T-8 circuit is operated at high speed, the charging time (acquisition time) is
The proportion of the cycle time increases.

When the T-8 circuit is used as an AD conversion circuit, the AD conversion operation is performed during hold. The longer the acquisition time is, the shorter the hold period will be.

Therefore, since the AD conversion operation must be performed within this short period, the operating speed required of the AC conversion circuit becomes severe, which is a problem.

On the other hand, if sufficient acquisition time is not taken in order to avoid the above problems, a problem arises in which the hold voltage accuracy in the T-8 circuit decreases.

An object of the present invention is to provide a T-8 circuit which has two sets of hold sections and which solves the above problems by alternately switching between them.

``Structure of the Invention'' [Means for Solving the Problems] In order to solve the above problems, the present invention provides an input stage amplifier having an inverting/non-inverting input terminal and to which an analog input signal is applied; 2! A circuit consisting of a capacitor whose charging voltage changes according to the output signal of the input stage amplifier, and a buffer amplifier that outputs a signal based on this capacitor voltage. A sample switch that switches and applies the output signal of the input stage amplifier to the two sets of circuits; and an output changeover switch that switches and outputs the output signal of the two sets of circuits between track and hold. It is designed to have the following.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing a T/T1 circuit according to the present invention in functional blocks, and FIG. 2 is a diagram showing a specific example of the configuration of FIG. 1.

In FIG. 1, 1 is an input stage amplifier, swl.

sw2 is a sample switch, CI and C2 are hold capacitors, 2 and 3 are buffer amplifiers, and sw3.

sw4 is an output changeover switch. Further, A is a control signal for selecting track mode/hold mode, and S
T is the output during tracking, and SH is the output during hold.

The input stage amplifier 1 has two input terminals, inverting and non-inverting, and its output is applied to hold capacitors C+ and C2 via sample switches swl and sw2.

The voltages of the capacitors C+ and C2 are introduced into buffer amplifiers 2 and 3 of low input current.

The outputs of the buffer amplifiers 2 and 3 are controlled by the output selector switch sw.
3, taken out via sw4. In addition, switch S
The helmets 1 to sw4 are turned on and off by the control signal A! I
IIIl].

In FIG. 2, 1 is an input stage amplifier, which corresponds to the input stage amplifier 1 in FIG. The input stage amplifier 1 in FIG. 2 outputs differential outputs 1 and 1 to the next stage.

01 to Q8 are transistors, each pair of transistors Q1 and C3, C2 and C4, whose collectors are connected to each other.
, . . . form one transistor current switch with each bare. That is, QI and 03 correspond to the number switch sw1 in FIG. 1, and C2 and C4 correspond to sw2. In addition, C6 and Qe are the output changeover switches sw in Fig. 1.
3, and C5 and Qv correspond to sw4. Capacitors C1 and C2 correspond to capacitors CI and C2 in FIG.

Also, FET J+ and resistor R1, FET J2 and resistor R
2 corresponds to the low input current buffer amplifier 2.3 in FIG. Zener diode D+.

D2 and resistors R3 and R4 are circuits that level shift the control signal A. Note that in FIG. 2, two logic signals a and a constitute the control signal A.

Differential output 1 of input stage amplifier 1. l is the transistor Q+
and are introduced into the emitters of C2, C3 and C4. Ql and Q
The collectors of C2 and C4 are connected to each other, and Q
The collectors of l and Q) are capacitor C1 and FET J+
connected to the gate.

Also, the collectors of C2 and C4 are capacitor C2 and FET.
Connected to the gate of J2. The sources of the two FETs J+ and J2 are connected to voltage VEE2 via resistors R1 and R2. The hold capacitor C+, C2
The other end is also connected to this voltage VEE2. FET J
The drain of l is connected to the emitters of transistors Q5 and C6, and the drain of J2 is connected to the emitters of C7 and Qa.

Further, the bases of Ql, C5, and day 0 are connected to each other, and a control signal i is applied thereto. Further, the bases of C2, 06, and 07 are also connected to each other, and the control signal a is applied thereto. Note that this control signal a is applied to the base of the transistor Q3 via the Zener diode D1, and the control signal a
is added to the base of C4 via D2. The bases of C3 and 04 are connected to voltage VEEI via resistors R3 and R4.

The collectors of transistors Q6 and QB are connected, and track output ST is taken out from there. The collectors of C5 and C7 are also connected, and the hold output SH is taken out from there.

The present invention will be explained in detail using FIG. The sample switches swl and sw2 are turned on and off alternately. now,
If sw2 is on and swl is off, the capacitor C2 changes every moment according to the signal level from the input stage amplifier 1. This capacitor voltage is taken out via buffer amplifier 3 and sw3. The signal taken out from this output changeover switch sw3 corresponds to the change in the signal of the input stage amplifier 1, and is the track output ST. on the other hand,
The voltage immediately after the sample switch sw1 is turned off is held in the capacitor C+. This voltage is taken out via buffer amplifier 2 and sw4. The signal taken out from this output selector switch SV [switch sw
This is the voltage immediately after 1 is turned off, and the hold output SH
It is. That is, track outputs ST and So are taken out.

Hereinafter, the present invention will be specifically explained in detail using FIG. 2. When the control signal a is 'high' and the control signal B is 'low', transistors Q+, C3, Qs, and C7 are turned on, and transistors C2, C4, C5, and C8 are turned off.

Therefore, the capacitor C7 is driven by the input stage amplifier 1, and the voltage VCI between its terminals is buffered by Jl.
Then, a current corresponding to the capacitor voltage MCI flows through the transistor Q6 and becomes the track output ST. On the other hand, transistor Q2. Since Q4 is off, capacitor C2 is
The voltage when C2 and Q- are turned off is held. This capacitor voltage VC2 is buffered by J2, and a current corresponding to the capacitor voltage VC2 flows through the transistor Q7 and becomes a bold output SH.

When the circuits shown in FIGS. 1 and 2 are used in the input stage of an AD converter, they are connected as shown in FIG. 4, for example. T- in Figures 1 and 2) (The circuit can be represented by a block as shown in Figure 3. In Figure 4, the track output is connected to the resistor RL.
+, the hold output is applied to the voltage V via resistor RL2.
Connected to F.

Further, the hold output is taken out via the buffer 5.

FF like this! In Figure 4, if the gain of the input stage amplifier 1 is sufficient, the potentials of the inverting input terminal (-) and the non-inverting input terminal (+) are equal, so the resistor RL+ has a current ILI of the following equation. Since this current ILI is sunk by the FET Jl shown in FIG. 2, the terminal voltage MCI of the capacitor C+ is finally expressed by the following equation.

Vc+ =R+ rt+ +Vos+Here, Vo
s + is the voltage between the gate and source of FET Jl.

Next, when the control signal A (a, a'') is inverted, the on/off states of the transistors Qma to Q8 are inverted.

That is, since Q+ + C3 is turned off, capacitor C
The terminal voltage VCI of 1 is held, and the final output current IL+ during tracking flows through C5 to the resistor RL2 as a hold output. If RL1=RL2, then the output is equal to the final value of the analog input signal V.

Figure 5 is a time chart of the circuit in Figure 2, including the hold capacitors C+, C2 and buffer amplifier J in Figure 2.
+, J2 operates to alternately repeat track and hold.

FIG. 6 is a diagram showing another groove formation example of the present invention.

This figure shows that according to the present invention, a plurality of (two in FIG. 6) hold outputs with the same characteristics can be easily generated.
1 to Q4, the Zener diode DI+C2*resistor R3, and Pa are not shown in FIG.

The relationship between FIG. 6 and FIG. 2 will be explained. In terms of components,
A transistor Tr+=Tra, resistors r1 to r5, and an amplifier U are newly provided. In terms of connections, the newly provided Tr5 to Trs are the same connections as 05 to Q8 in Figure 2.
The operation is performed, and a hold output Su=1q is output from the collectors of Tr5 and Try. Note that in FIG. 6, this hold output SH- is taken out from the amplifier U, but this amplifier U may be omitted. Further, a track output ST is obtained from the collectors of Trs and Tra.

Normally, the circuits shown in FIGS. 2 and 6 are connected as shown in FIG. 4, so that the track output ST is fed back to the inverting input terminal (-). In the case of FIG. 6, since it is sufficient that one of the two track outputs ST be fed back to the inverting input terminal, the collectors of Tra and Tra are connected to the circuit ground.

In addition, in Fig. 2, FETs Jl and J2 are directly connected to the emitters of transistors 05 to Qe, but in Fig. 6, these J
In place of J2, transistors Tr+ to Tra are provided. Then, FE is applied to the base of Tr1 to Tr4.
Connect the sources of T J+ and J2, and connect T r I to T
I try to drive ra. In addition, J+
, J2 are connected to circuit ground.

With this configuration, a plurality of hold outputs with uniform characteristics can be obtained. A T-8 circuit such as that shown in FIG. 6 is particularly useful in two-step high speed analog/digital conversion circuits. To explain the reason, generally, a two-step high-speed analog/digital conversion circuit includes a first AD converter that converts the upper digits of the input signal into digital;
a second A that converts the remaining lower digits of the input signal to digital;
Equipped with a D converter. If the input stages of these two AD converters were driven by one T/T1 circuit, interference could occur due to the output impedance of the T/8 circuit.
According to the circuit shown in FIG. 6, such a problem does not occur.

C. E Effects of the Invention As described above, according to the present invention, the input stage amplifier can share the input part of the two hold capacitors, and by performing feedback, the input part of the two hold capacitors can be shared. Since the characteristics can be made uniform, a T-8 circuit with a high opening degree can be realized.

In addition, two sets of hold capacitors are provided, and these are used alternately, allowing for a longer track period.
Easy to speed up.

In addition, as shown in FIG. 2, as switches sw1 to sw4,
Since a current switch can be used, speeding up can be easily achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the block configuration of a T-8 circuit according to the present invention, FIG. 2 is a diagram showing a specific example of the configuration of FIG. 1, and FIG. 3 is a diagram representing FIG. 2 in blocks. , Figure 4 is T-1
Figure 5 is a time chart of the present invention; Figure 6 is a diagram showing another example of the configuration of the T-8 circuit according to the present invention. It is. 1... Input stage amplifier, 2, 3... Buffer amplifier,
sw1-sw4...switch, C+, C2...capacitor, R1-R4...resistance, r1-r5...resistance, 01-QB...transistor, Tr+-Tr
a...transistor, J blind IJ2
...FET.

Claims (1)

[Claims] An input stage amplifier having an inverting/non-inverting input terminal and to which an analog input signal is applied; a capacitor whose charging voltage changes according to the output signal of the input stage amplifier; and a capacitor whose charging voltage changes based on the capacitor voltage. 2 sets of circuits, each consisting of a buffer amplifier that outputs a signal from the input stage amplifier, a sample switch that switches and applies the output signal of the input stage amplifier to the 2 sets of circuits, and a sample switch that outputs the output signal of the 2 sets of circuits when tracking A track/hold circuit characterized in that it is equipped with an output changeover switch that switches and outputs output depending on whether it is held or not.