JP2533109B2 - Waveform synthesis circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a waveform synthesizing circuit used as, for example, a D / A exchanger or the like.

(Prior Art) As a conventional waveform synthesizing circuit used as a D / A converter or the like, for example, there is one as shown in FIG. In the figure, CΦ is a capacitor for initial level setting, C1 to CN are capacitors for setting each level of output waveform, and one end of the capacitor CΦ for initial level setting and one of capacitors C1 to CN for setting each level of output waveform Commonly connected to the output signal line 11. Output waveform Capacitor C1 for each level setting
The CN has a capacitance corresponding to each level of the output waveform, and the initial level setting capacitor CΦ is
Output waveform A capacitor with a larger capacity than the capacitors C1 to CN for setting each level is used. Output waveforms Each capacitance value of the capacitors C1 to CN for setting the level defines the voltage level amount of 1 LSB (minimum digit) in the output waveform as described later.

Reference numeral 12 is an input terminal for the power supply voltage Vcc, 13 is a ground terminal, the input terminal 12 for the power supply voltage Vcc is connected to the output signal line 11 via the switch SWФ for initial level setting, and another capacitor CФ for initial level setting The end is connected to the ground terminal 13. The above-mentioned power supply voltage Vcc defines the maximum level of the output waveform.

The other ends of the output waveform level setting capacitors C1 to CN are connected to the switching contacts c of the changeover switches SW1 to SWN, respectively. , And the other fixed connection b is commonly connected to the ground terminal 13.

The changeover switches SW1 to SWN are driven and controlled by the input binary code signal shown in FIG. 6, and the other ends of the capacitors C1 to CN for setting the output waveform levels are connected to the input terminal 12 of the power supply voltage Vcc.
Alternatively, it is switched and connected to the ground terminal 13. Sixth
Binary code signal diagram, the example timing t ₁ '1,
"0,0,0, ..." is inputted to the waveform synthesizing circuit, and the signal of each bit from the MSB (most significant digit) bit in the binary code signal is supplied to the changeover switches SW1 to SWN. . Then, the changeover switch to which the signal of the "1" level bit is inputted is controlled to change from the fixed contact a to the fixed connection b.

Reference numeral 14 is a buffer, and 15 is an output terminal. The buffer 14 is supplied with voltages from two power sources of + V _DD and −Vee.

Initially, the changeover switches SW1 to SWN are changed over to the fixed contact a side, and the power source Vcc is supplied to the other ends of the capacitors C1 to CN for setting the output waveform levels. In this state, switch SW for initial level setting as shown in FIG.
When Φ is once turned on and then turned off, the power supply voltage Vcc is charged in the initial level setting capacitor CΦ. At this time, the capacitors C1 to CN for setting each level of the output waveform are not charged because both ends have the same potential at the power supply voltage Vcc.

Next, as shown in FIG. 6, first, at the time of t _1, a binary code signal of “1, 0, 0, 0, ...” Is input and only the changeover switch SW1 is changed by the “1” level signal of the MSB. When turned on, the other end of the first-stage capacitor C1 for setting each output waveform level shifts to the ground level, and the electric charge stored in the initial-level setting capacitor CФ is distributed to this first-stage capacitor C1. The capacitor C1 is also charged.

At this time, since the total amount of charge Q before and after the changeover switch SW1 is turned on does not change, the capacities of the first stage capacitor C1 and the initial level setting capacitor Cφ are respectively
If C1 and Cφ are used and the total capacity of the capacitors including them is expressed as C, the voltage level of the output signal line 11
V1 is given by the following equation.

V1 = Vcc (1 / C1 / V) (1) In this way, by adding the capacity of the initial capacitor C1 for setting the output waveform to the capacity of the initial level setting capacitor CФ, the output signal Voltage level of 1 LSB
Only drops. Then, for example, "1, 1,
"0,0, ...", "1,1,1,0, ..." Binary code signals are input, the changeover switches SW2, SW3 are sequentially turned on, and the second stage for setting each level of the output waveform, The three stages of capacitors C2 and C3 are sequentially charged to set the respective levels of the output waveform, and the staircase output waveform corresponding to the input binary code as shown in FIG. Taken from.

The extracted staircase output waveform is passed through a low-pass filter (not shown) to be an analog signal having a curved waveform as shown in FIG.

(Problems to be Solved by the Invention) In the conventional waveform synthesizing circuit, the maximum level of its output waveform is defined by the power supply voltage Vcc, and each level is set with reference to this power supply voltage Vcc. For this reason, the center level of the output waveform becomes uncertain, and setting or processing of the voltage level of each device connected to the latter stage of the waveform synthesis circuit becomes complicated, and the power supply voltage V _DD of the buffer 14 is the power supply voltage in the waveform synthesis circuit. V _DD > Vcc must be set for the voltage Vcc, and a separate power supply is required. Further, in the case of amplifying the synthesized output waveform, there is a problem that it is necessary to perform a capacitor coupling, then apply a central bias voltage externally, and then process it with an operational amplifier or the like.

And in the conventional waveform synthesis circuit, even if the power supply voltage Vcc and the ground potential are exchanged, the minimum level of the output waveform is specified by the ground potential at this time, and each level is set with this ground potential as a reference. Similarly, the center level of the output waveform becomes uncertain.

The present invention has been made under the above circumstances, and an object thereof is to provide a waveform synthesizing circuit capable of fixing the central level of an output waveform to a reference potential.

[Structure of the Invention] (Means for Solving Problems) In order to solve the above problems, the present invention has one end connected to a high voltage source and a low voltage source via a first switch, A plurality of capacitors, the other ends of which are connected to the output signal line, are provided in parallel, and each of the switches is switched between two states, and in one state, one end of the corresponding capacitor is connected to the high voltage source. In the other state, one end of the corresponding capacitor is connected to the low voltage source in the other state, and the output signal line has a voltage having an intermediate potential between the high voltage source and the low voltage source via the second switch. Source, the second switch is closed once, the output signal line is set to the intermediate potential, and then the second switch is opened to input the binary code signal to the first switch. Control each bit signal One end of a predetermined capacitor in the capacitors is selectively connected to one of the high voltage source and the low voltage source, and one end of the remaining capacitors in the capacitor is connected to the high voltage source and the low voltage source. And the potential of the output signal line connected to the other of the sources is a potential corresponding to the binary code signal between the high voltage source and the low voltage source centered on the intermediate potential. To do.

(Operation) One end of the plurality of capacitors for setting the output waveform levels is initially set to the reference potential by the reference potential setting means. Next, the switches connected to the other ends of the plurality of capacitors are sequentially driven and controlled by the input binary code signal, and the first bias voltage set higher by the required potential difference and the second bias set lower than the reference potential. Bias voltage is switched and supplied to the other ends of the plurality of capacitors.
By switching and supplying the first bias voltage and the second bias voltage to the other end of each capacitor, each level of the output waveform corresponding to the input binary code signal is set with the reference potential as the reference, and the output signal A synthetic output waveform centered on the reference potential is output from the line.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

First, the configuration of the waveform synthesizing circuit will be described. C _{1 in} FIG.
~Cn, Cn ₊₁ ~C ₂ n is a capacitor for each level setting output waveform, one end of these capacitors the output signal line 1
Are commonly connected to. Capacitor C ₁ to Cn for setting each output waveform level, Cn ₊₁ -C ₂ n, it is used as a capacity corresponding to each level of each output waveform in the output waveform, as will be described later by their respective capacitance values The voltage level for 1 LSB of is specified.

Cφ is an initial potential setting capacitor, one end of this initial potential setting capacitor Cφ is connected to the input terminal 2 of the reference voltage Vref, and the other end is connected to the output signal line 1. An initial potential setting switch SWφ is connected in parallel to the initial potential setting capacitor Cφ. By turning on the initial potential setting switch SWφ, the capacitors C ₁ to Cn and Cn _{+1 to} C ₂ n for setting the output waveform levels are charged with the reference voltage Vref, and one end of the capacitors is initialized to the reference potential. Is set. Thus, the reference potential setting means is composed of the initial potential setting capacitor Cφ and the initial potential setting switch SWφ.

3 is a first bias voltage source, 4 is a second bias voltage source, and the reference voltage Vref is supplied from the first bias voltage source 3.
, The first bias voltage Vb ₁ set higher than the required potential difference is output, and the second bias voltage source 4 outputs the _second bias voltage Vb ₂ set lower than the reference voltage Vref by the required potential difference. To be done.

A plurality of capacitors for setting the output waveform levels are provided in the first group C _{1 to} Cn and the second group Cn + _1.
~ C ₂ n and each capacitor C ₁ of the first group
The other end of ~Cn, each constantly through the switch SW ₁ ～SWn the first bias voltage Vb ₁ from a first bias voltage source 3 is supplied. The changeover switch SWn is provided at the other end of each of the capacitors Cn _{+ 1 to} C2n of the _second group.
The second bias voltage Vb ₂ from the second bias voltage source 4 is constantly supplied via _{+1 to} SW ₂ n.

The changeover switches SW _{1 to} SWn and SWn _{+1 to} SW ₂ n are drive-controlled by the "1" level signal in the input binary code signal, and the changeover switches SW _{1 to} SWn and SWn _{+1 to} SW ₂ By the switching operation of n, the capacitors C _{1 to} Cn of the first group
The second bias voltage Vb ₂ is switched and supplied to the other end of the
At the other end of each of the capacitors C n _{+1 to} C ₂ n of the second group,
The first bias voltage Vb ₁ is switched and supplied.

Thus, each of the capacitors C _{1 to} Cn of the _first group has a function of synthesizing a waveform having a level lower than the reference voltage Vref in the output waveform of FIG. 4, and each capacitor of the second group. cn ₊₁ -C ₂ n has a composite function of the level of the waveform above the reference voltage Vref.

 Reference numeral 5 is a buffer similar to the above, and 6 is an output terminal.

Next, the operation will be described with reference to FIGS. However, it is assumed here that the capacitor Cφ is a stray capacitance associated with the switch SWφ and can be ignored as compared with C ₁ -C _2n .

When the initial potential setting switch SWφ is first turned on and then turned off, the reference voltage Vref is transmitted to the output signal line 1 and a plurality of capacitors C ₁ to
Cn, one end of the Cn ₊₁ -C ₂ n is set to the reference potential. FIG. 3A shows an equivalent circuit of the circuit of FIG. 1 set to the reference potential. However, here
The parasitic capacitance C0 is small and can be ignored. In this state, each of the capacitors Cn ₊₁ -C ₂ n of the first of the capacitors C ₁ to Cn and second group of the group are all parallel connection state within each group. Third
In (a) of the figure, C ₀₁ represents the sum of the capacities of the capacitors C _{1 to} Cn in the first group, and C ₀₂ represents the sum of the capacities of the capacitors C n _{+1 to} C ₂ n in the second group. Shows.

Then, as shown in FIG. 2, the first stage of switching in the first group by the "1" level signal of the binary code signal is inputted that the MSB of "1, 0, 0, 0 ..." at timing t ₂ Only the switch SW ₁ is turned on, and the second bias voltage Vb ₂ is switched and supplied to the other end of the _first- stage capacitor C ₁ . Thus the first stage of the bias state of the capacitor C ₁ in the first group, the same as the bias condition of each of the capacitors Cn ₊₁ -C ₂ n of the second group, the capacitor C ₁ of the first stage of the first group is the It will be as if it had been moved to the group 2 side.

FIG. 3 (b) shows this state, and the total capacitance of the capacitors of the second group is equivalently C ₀₂ + C ₁ ,
The total capacitance of the capacitors of the first group is C ₀₁ -C _1. Therefore, the charge charge at the reference potential point in FIG.
If Q ₀ , this charge Q ₀ does not change even if it shifts to the state of FIG. 3 (b), so the potential V 01 of the output signal line 1 becomes
It changes as shown by the following equation with respect to the set reference voltage Vref.

V ₀₁ = {Vref (C ₀₁ + C ₀₂ ) -C ₁ (Vb ₁ -Vb ₂ )} / (C ₀₁ + C ₀₂ ) ……
(2) Note that the equations including the case of Q0 ≠ 0 are also saved even when the charge of the output signal line 1 changes from the state of FIG. 3 (a) to the state of FIG. 3 (b). It is easily obtained from the condition that it is done, and becomes as follows.

V ₀₁ = {Vref (C ₀ + C ₀₁ + C ₀₂ ) -C ₁ (Vb ₁ -Vb ₂ )} / (C ₀ + C ₀₁ + C
₀₂ ) (3) In this way, the potential of the output signal line 1, that is, the level of the output waveform fluctuates in the direction of decreasing by the level corresponding to the capacitance of the first stage capacitor C ₁ of the first group.

Then, subsequently, for example, “1, 1, 0, 0, ...”,
When a binary code signal of "1, 1, 1, 0, ..." is input, the second bias voltage Vb ₂ is sequentially switched and supplied to the other ends of the second and third stage capacitors in the first group. The output waveform level to a level below the reference voltage Vref.
V ₀₂ and V ₀₃ are set sequentially.

In this way, the capacitors C _{1 to} Cn of the first group
2 code signal "0, 0, which corresponds After entering, the second group at a timing t ₃ of the binary code signal corresponding to ...,
, 1, 0, 0, 0, ... "is input, the first-stage changeover switch SWn ₊₁ in the second group is turned on by the" 1 "level signal in the binary code signal, and the first-stage capacitor Cn _{+ 1} is switched and supplied to the other end of the first bias voltage Vb ₁ .

Therefore, at this time, contrary to the above, the first stage capacitor Cn ₊ 1 of the second group is moved to the first group side, and the level Vn _{1 of the} output waveform is equal to the reference voltage Vn _1.
With respect to ref, it fluctuates in the direction of increasing by a level corresponding to the capacitance of the first-stage capacitor Cn _{+ 1} of the second group.

After that, as in the case of the first group, “0,
0, ..., 1,1,0,0, ... "," 0,0, ... 1,
By inputting a binary code signal of "1, 1, 0, ...", each level of the output waveform becomes Vn ₂ , V
n ₃ are set sequentially.

In this way, the staircase-shaped output waveform corresponding to the binary code having the reference potential as the center level is taken out from the output terminal 6 via the buffer 5. The staircase output waveform is passed through a low-pass filter (not shown) to be an analog signal having a curved waveform as shown in FIG.

As described above, according to the present invention, each level of the output waveform corresponding to the input binary code signal is set with reference to the reference potential initially set by the reference potential setting means. Therefore, the output signal line outputs a combined output waveform centered on the reference potential. Therefore, it becomes easy to set or process the voltage level of each device connected to the latter stage of the waveform synthesis circuit, the power source of the buffer etc. can share the power source of the waveform synthesis circuit, and if the synthesized output waveform is amplified, It has the advantage that it can be directly connected to the amplifier.

[Brief description of drawings]

1 to 4 show an embodiment of a waveform synthesizing circuit according to the present invention. FIG. 1 is a circuit diagram showing the entire configuration, and FIG. 2 is a timing chart showing an example of an input binary code signal. FIG. 3 is a diagram for explaining the action of setting each level of the output waveform corresponding to the input binary code signal,
FIG. 4 is a waveform diagram of a synthetic output waveform, FIG. 5 is a circuit diagram of a conventional waveform synthesizing circuit, FIG. 6 is a timing chart of an input binary code applied to the conventional example of the above, and FIG. 7 is a conventional example of the above. 5 is a waveform diagram of a combined output waveform according to FIG. 1: output signal line, 2: reference voltage input terminal, 3: first bias voltage source, 4: second bias voltage source, Cφ: initial potential setting capacitor, C _{1 to} Cn: first group Output waveform level setting capacitors, Cn _{+1 to} C ₂ n: Second group output waveform level setting capacitors, SWφ: Initial potential setting switch, SW _{1 to} SW ₂ n: Changeover switch.

Claims (2)

(57) [Claims] 1. A plurality of capacitors each having one end connected to a high voltage source and a low voltage source via a first switch and the other end connected to an output signal line are provided in parallel, and the switch is provided. Each switching between two states, one end of the corresponding capacitor being connected to the high voltage source in one state and one end of the corresponding capacitor being connected to the low voltage source in the other state, The output signal line is connected via a second switch to a voltage source having an intermediate potential between the high voltage source and the low voltage source, the second switch is closed once, and the output signal line is at the intermediate level. Of the input binary code signal is applied to the first switch as a control signal, and one end of a predetermined capacitor of the capacitors is set. Is selectively before One of a high voltage source and the low voltage source is connected, one end of the remaining capacitor in the capacitor is connected to the other of the high voltage source and the low voltage source, and the potential of the output signal line is the intermediate potential. Waveform synthesizing circuit having a potential corresponding to the binary code signal between the voltage source and the low voltage source centered on 2. The waveform synthesizing circuit according to claim 1, wherein the output signal line is connected to a buffer circuit.