JP3176860B2 - Signal transmission circuit, signal transmission method, A / D converter, and solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit and method for efficiently transmitting a signal using a signal line having a parasitic capacitance, and an A / A for converting an analog signal to a digital signal.
The present invention relates to a D converter and a solid-state imaging device that generates an output signal corresponding to an input image.

[0002]

2. Description of the Related Art An A / D converter is used to convert an analog signal into a digital signal. As the circuit configuration of the A / D converter, for example, a successive approximation type, a serial-parallel type, and a fully parallel type are used. These schemes have advantages and disadvantages in terms of conversion speed, conversion accuracy, and power consumption, respectively.

Of the three methods, the one with the highest conversion speed is the all-parallel type, which is the basic method of an A / D converter realized as an integrated circuit. Disadvantages of the all-parallel type include that the conversion accuracy and power consumption are not sufficiently satisfactory.

[0004] In recent years, there has been an increasing need to reduce the power consumption of portable electronic devices. As a result, A / D converters are increasingly required to have low power consumption. Therefore, a serial-parallel A / D converter is often used instead of the all-parallel type.

FIG. 23 shows a conventional serial / parallel A / D converter.
It is a block diagram showing a converter. The comparator 2310 receives the analog input signal Ain and compares it with the reference voltage sequence Ref. The comparator 2310 converts the higher digital value DU obtained as a result of the comparison into a DAC (D / A converter) 2330.
And an arithmetic circuit 2340. DAC2330
Is the higher digital value D output from the comparator 2310
Based on U, a lower reference voltage sequence RefL, which is a reference for determining lower bits, is output. Comparator 2320 compares lower-order digital value DL with lower-order reference voltage sequence RefL to calculate lower-order digital value DL by arithmetic circuit 2340.
Output to The arithmetic circuit 2340 calculates the upper digital value D
A / D conversion output value D from U and lower digital value DL
out is generated and output.

[0006]

In the A / D converter shown in FIG. 23, a digital signal DU output from a comparator 2310 is converted into an analog signal RefL by a DAC 2330. D / A in DAC2330
Conversion reduces conversion speed and increases power consumption. Therefore, without performing such D / A conversion, A
It is desirable that a / D converter can be realized. That is, it is desirable that the comparator 2310 outputs an analog signal to the comparator 2320.

However, the transmission of an analog signal leads to a decrease in operation speed and an increase in power consumption due to parasitic capacitance on a signal line. The main causes of the parasitic capacitance of the signal line are a large number of switches connected to the signal line and long signal lines. Circuits that drive signal lines with large parasitic capacitance
A large driving capability is required, and the power consumption increases.

As described above, when transmitting an analog signal, there is a problem that the operating speed and power consumption of the system are reduced due to parasitic capacitance. A / D converters that handle analog signals have the same problem. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a signal transmission circuit and a signal transmission method for transmitting an analog signal at high speed with a small driving capability via a signal line having a large parasitic capacitance. Transmission method and A / D
It is to provide a converter and a solid-state imaging device.

[0009]

According to a signal transmission circuit of the present invention, a transmission unit that receives an input signal transmits a signal to a reception unit via a signal line and outputs an output signal corresponding to the input signal. A transmission unit, wherein the transmission unit includes a first capacitive unit, a charge supply unit that supplies a charge corresponding to the input signal to the first capacitive unit, and a supply and stop of a charge from the charge supply unit. And a supply control unit for controlling the supply unit, wherein the receiving unit includes a second capacitive unit that receives the charge from the first capacitive unit, and the charge unit stores the charge accumulated in the first capacitive unit. A signal line for transmitting to the second capacitive means, a parasitic capacitive element on the signal line, and a transmitting means for controlling transmission and non-transmission of electric charge between the first capacitive means and the signal line Wherein the total capacitance value of the second capacitive means and the parasitic capacitance element is equal to the first capacitance value. Larger than the capacitance value of said transfer means charge supplying unit during non-transmission gives a charge to said first capacitive means, said supply control means during transmission is characterized by stopping the supply of the charge.

[0010] In one embodiment, the apparatus further comprises conversion means for generating an output signal corresponding to the electric charge transferred to the second capacitive means.

In one embodiment, the first capacitive means has a first terminal and a second terminal, the second capacitive means has a first terminal and a second terminal, and the transmitting means is A switch for changing a connection state between a first terminal of the first capacitive means and a first terminal of the second capacitive means,
A second terminal of the first capacitive means is connected to a second terminal of the second capacitive means.

In one embodiment, the charge supply unit has an amplifier, and the supply control unit has a switch unit connected between an output terminal of the charge supply unit and the first capacitive unit.

[0013]

In one embodiment, the conversion means includes the second capacitive means, and amplifies the signal at the input terminal and outputs the amplified signal to the output terminal.
A capacitive means connected to the input terminal and the output terminal;

In one embodiment, the conversion means has a variable capacity.

An A / D converter according to the present invention is an A / D converter that receives an input voltage and outputs a digital signal corresponding to the input voltage, the voltage corresponding to a difference between the input voltage and a reference voltage. Amplifying means, a holding capacitive means for holding a voltage output from the amplifying means, a signal line having a first terminal and a second terminal, a parasitic capacitive element on the signal line, First transmission means provided between the storage means and the storage capacitive means; second transmission means provided between the storage capacitive means and the first terminal of the signal line; A receiving capacitive means connected to a second terminal for receiving the retained charge of the retaining capacitive means, wherein in the first state, the first transmitting means is conductive, and the second transmitting means is Non-conducting, and in the second state, the first transmitting means is non-conducting; (2) The transmission means is conductive, and the time constant of the signal transmission speed is reduced by making the total capacitance value of the parasitic capacitive element and the receiving capacitive means larger than the capacitance value of the holding capacitive means. And

A signal transmission method according to the present invention is a signal transmission method for receiving an input signal and outputting an output signal corresponding to the input signal.
A transfer step of transferring the stored charge from the first capacitive means to the second capacitive means, wherein the stored charge is a signal. The signal is transferred from the first capacitive means to the second capacitive means via a transmission line, and the total capacitance of the parasitic capacitive element of the signal transmission line and the second capacitive means is the capacitance of the first capacitive means. In the transfer step, transmission and non-transmission of signals between the first capacitive means and the signal transmission line are controlled, and charge accumulation in the first capacitive means in the accumulation step is stopped. .

In one embodiment, the method further includes a conversion step of generating an output signal corresponding to the charge transferred to the second capacitive means.

[0019]

[0020] In one embodiment, the converting step includes:
An amplifier including the second capacitive means, amplifying a signal at an input terminal, and outputting the amplified signal to an output terminal;
A capacitive element connected to the input terminal and the output terminal is used.

In one embodiment, the step of converting includes:
Use variable capacitance.

A solid-state imaging device according to the present invention is a solid-state imaging device for receiving incident light and outputting an output signal corresponding to the incident light, wherein the first capacitive means and a charge corresponding to the incident light are charged. A charge supply unit to be provided to the first capacitive unit;
Capacitive means, a first terminal connected to one terminal of the first capacitive means, a second terminal connected to the second capacitive means, and stored in the first capacitive means. A signal line for transmitting the charged electric charge to the second capacitive means, a parasitic capacitive element on the signal line, and the other terminal of the first capacitive means and a predetermined potential, A transmission means for controlling transmission and non-transmission of the electric charge accumulated in the first capacitive means, wherein a total capacitance value of the parasitic capacitive element and the second capacitive means is equal to the first capacitive means. Is larger than the capacitance value.

In one embodiment, the charge supply section is a photodiode, and the first capacitive means is a parasitic capacitance of the photodiode.

[0024] In one embodiment, the apparatus further comprises conversion means for generating an output signal corresponding to the electric charge transferred to the second capacitive means.

In one embodiment, the conversion means includes the second capacitive means, amplifies the signal at the input terminal, and outputs the amplified signal to the output terminal; And a capacitive means connected to the output terminal.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present specification, "the switch is on" means that the switch is closed.
That is, when the switch is on, current flows through the switch. Conversely, "the switch is off" means that the switch is open. That is, when the switch is off, no current flows through the switch.

(Embodiment 1) First, a signal transmission circuit and a signal transmission method of the present invention will be described.

FIG. 1 is a diagram showing the principle of a signal transmission circuit and a signal transmission method according to the present invention. The signal transmission circuit of the present invention includes a transfer unit 100 and a conversion unit 200. The transfer unit 100 outputs a charge corresponding to the input signal to the conversion unit 200. The conversion unit 200 receives the charge,
A signal corresponding to the received charge is output.

The capacitance C1 is, for example, a stray capacitance due to wiring between the transfer unit 100 and the conversion unit 200, but is not limited to this. The capacitance C1 may be any capacitive load generated between the signal line connecting the transfer unit 100 and the conversion unit 200 and the ground. That is, the capacitance may not be due to discrete components such as the stray capacitance of the wiring or the capacitance of an electronic switch connected to the transfer unit 100, or may be due to discrete components such as a chip capacitor. The capacity may be used.

The transfer section 100 has a capacitance C0, a resistor R, and a switch S, which are connected in series. When the switch S is off (that is, when the switch S is open), the capacitor C0 includes a charge supply unit (not shown).
Gives the charge Q0. In the initial state in which the switch S is off, the capacitors C1 and C2 do not store charge, and the potential difference between the capacitors C1 and C2 is assumed to be zero. The switch S is turned on (that is, the switch S is closed) when transferring the charge Q0 to the conversion unit 200. The resistance R is the capacitance C0 and the capacitances C1 and C
2 represents a resistance existing between the switch S and the switch S.

When the switch S is turned on from off, the charge Q0 stored in the capacitor C0 moves to the capacitors C1 and C2. When the switch S is on, the potential difference between both ends of the capacitor C1 and the potential difference between both ends of the capacitor C2 are set to ΔV. Here, it is assumed that the capacitance (C1 + C2) is sufficiently larger than the capacitance C0. At this time, from the viewpoint of the capacitance C0, the capacitance (C1 + C2) looks like a ground. In other words, it can be considered that the capacitance C0 is short-circuited via the resistor R.

FIG. 2 is an equivalent circuit diagram of the circuit of FIG. 1 when (C1 + C2) >> C0 holds. In the circuit of FIG. 2, since the charge Q0 stored in the capacitor C0 is discharged via the resistor R, the time constant is equal to C0 · R. To realize high-speed signal transmission, the time constant C0 · R
Needs to be smaller. Here, the resistance R is the resistance of the conventional switch S. Therefore, the time constant C0 in FIG.
It can be seen that the value of the capacitance C0 should be set small in order to reduce R. According to the present invention, by setting the capacitance C0 small, the time constant C0 · R can be sufficiently increased.
It is possible to make it smaller.

That is, in the present invention, (C1 + C
2) By satisfying the relationship of C0, low-power and high-speed signal transmission is possible. Further, by reducing the capacitance C0, there is an effect that even if the driving force of the input signal source is small, it can be connected to the signal transmission circuit of the present invention. Further, transferring the charge stored in the capacitor C0 to the capacitors C1 and C2 and distributing the charge includes:
Since no noise is generated, S is smaller than that of the conventional signal transmission circuit.
/ N ratio can be improved.

Referring again to FIG. When the switch S is on, the charge Q0 stored in the capacitor C0 is distributed to the capacitors C1 and C2. According to the above assumption, all the charges Q0 move to the capacitors C1 and C2. Under this assumption, the voltage ΔV generated at the terminal A is almost zero. Equations 1 and 2 below for the capacitances C1 and C2
Holds.

Δq1 = C1 · ΔV (Equation 1) Δq2 = C2 · ΔV (Equation 2) Here, Δq1 and Δq2 indicate electric charges stored in the capacitors C1 and C2, respectively.

When the voltage ΔV is eliminated from the equations (1) and (2), the following equation (3) is obtained.

Δq1 / Δq2 = C1 / C2 (Equation 3) As is apparent from Equation 3, the ratio of the capacitance C1 to the capacitance C2 is equal to the ratio of the charge Δq1 to the charge Δq2. Therefore, if the capacitance C2 is sufficiently larger than the capacitance C1,
Almost all of the charge Q0 is stored in the capacitor C2. This means that, according to the present invention, the charge Q0 can be transferred from the capacitor C0 to the capacitor C2 without being affected by the capacitance C1 (for example, due to the stray capacitance or the like). It means something. Therefore, in the present invention, it is preferable that the capacitance C2 is larger than the capacitance C1.

Next, the charge supply unit in the signal transmission circuit and method according to the present invention will be described.

FIG. 3 is a circuit diagram showing an example of a charge supply section for supplying a charge Q0 to the capacitor C0. Charge supply unit 300
Are a complementary connected P-channel FET (field effect transistor) 302 and an N-channel FET 304
And When the gates of the FETs 302 and 304 are set to H (high level), a charge is supplied from the power supply VDD to the capacitor C0. The circuit in FIG. 3 is an inverter using an FET, but is not limited to this. Charge supply unit 300
May have a configuration different from that of the above-described circuit as long as it is a driver amplifier that controls the electric charge from the power supply and supplies it to the capacitor C0.

FIG. 4 is a circuit diagram showing a charge supply unit using a diode. The charge supply unit 300 includes a diode D
i. If the diode Di is reverse biased, a junction capacitance is formed in the diode Di. This junction capacitance can be used as the above-mentioned capacitance C0. When light is applied to the junction of the diode Di, charges are generated at the junction. This charge can be used as the charge Q0 in FIG. The circuit in FIG. 4 uses a diode, but is not limited to this. The charge supply unit 300 may be another element as long as it is a semiconductor element that generates charges by light.

Further, the conversion unit 200 in the signal transmission circuit and method according to the present invention will be described.

FIG. 5 is a circuit diagram showing an example of the conversion unit 200. 5 includes an inverter 202, a capacitor 204, and a switch 206. Inverter 2
02 has an amplification factor G. Here, the amplification factor G is negative. That is, assuming that the input voltage is Vi and the output voltage is Vo, Vo = G · Vi, and the output voltage Vo has the opposite phase to the input voltage Vi. An input terminal and an output terminal of the inverter 202 are connected to two terminals of the capacitor 204. The capacitance of the capacitor 204 is C2f.

In the circuit of FIG. 5, the apparent capacitance when viewed from the terminal A is (-G + 1) .C2f. This is, as will be described in detail later using equations, the inverter 20.
2 due to the negative feedback operation. Therefore, even if the capacitance C2f is small, the capacitance seen from the terminal A becomes large because the inverter 202 is connected to the capacitance 204 in parallel. This capacitance (−G + 1) · C2f corresponds to the capacitance C2 in FIG.
In the circuit of FIG. 5, the charge Q given from the capacitor C0
0 is transferred to the capacity 204 and the inverter 2
02 and then output to terminal B. Therefore, a voltage corresponding to the applied charge Q0 is output from the terminal B. By operating the circuit shown in FIG. 5, a step of transmitting a signal (that is, a step of transferring a charge) and a step of reading a signal are performed simultaneously. As a result, there is an effect that the time required for signal transmission can be reduced.

FIG. 6 is a circuit diagram of a converter 200 using a variable capacitor. The conversion unit 200 has a variable capacitance VC. The variable capacitance VC can change its capacitance value by external control. Terminal A receives charge Q0 and outputs a voltage corresponding to charge Q0.

When the charge Q0 is transferred from the capacitor C0 to the capacitor VC, the value of the capacitor VC is sufficiently compared with the value of the capacitor C0.
Set larger. When the charge Q0 is read out from the terminal A as the output voltage after the transfer of the charge Q0, the value of the capacitance VC is set small. Before and after the charge transfer, the ratio of the capacitance VC to the capacitance C0 changes from large to small. as a result,
The voltage at the terminal A also increases (that is, the potential difference between both ends of the capacitor VC increases). Thus, according to the present invention, the charge Q
It is convenient to read the voltage corresponding to 0, that is, the output signal to the outside. Note that in order to operate the circuit illustrated in FIG. 6, a step of transmitting a signal (that is, a step of transferring a charge) and a step of reading a signal are sequentially performed. The circuit of FIG. 6 has the effect that the voltage corresponding to the transferred charges can be boosted without deteriorating the S / N ratio.

(Embodiment 2) FIG.
It is a block diagram of a D converter. The upper amplifier row 710 is
It receives the analog input signal Ain and a plurality of reference voltages Ref, amplifies the difference between the analog input signal Ain and the reference voltage Ref, and outputs the amplified signal. The lower amplifier array 720 selects only the reference voltage near the voltage of the analog input signal Ain from the reference voltage Ref, and outputs the lower bit data DL by interpolating the selected reference voltage.
Amplifier array 730 outputs higher-order bit data DU indicating which of the sections defined by a plurality of reference voltages Ref the analog input signal Ain belongs to.
Arithmetic circuit 740 collects data DU and data DL, and finally converts converted digital data Dout corresponding to the voltage of the input analog signal.
Is output.

As shown in FIG. 7, the A / D converter according to the present invention differs from the A / D converter according to the prior art in that the D / A
No conversion unit. Thereby, the power consumed by the D / A converter can be reduced. When the A / D converter according to the present invention is integrated, the chip size can be reduced. This is because the chip area occupied by the D / A converter is large.

FIG. 8 is a circuit diagram of an A / D converter according to the present invention. Among the reference symbols in FIG. 8, a, b,
Elements of the same number with the alphabets c,... have the same circuit configuration. For example, the first amplifier circuits 6a to 6i included in the first amplifier circuit row 5 have the same circuit configuration. Further, for example, when the first amplifier circuits 6a to 6i are collectively referred to, the last alphabet is omitted, such as simply “first amplifier circuit 6”.

In FIG. 8, the reference numerals of the terminals (terminals indicated by one letter of the alphabet) of the elements having the same circuit configuration are given to only one representative to avoid complexity. For example, the first amplifier circuit 6 has terminals a, b, c, and y, but these reference numerals are assigned only to the first amplifier circuit 6a, and the first amplifier circuits 6b to 6i are assigned. Absent.

The constant voltage source 1 applies the voltage Vr1 and the constant voltage source 2 applies the voltage Vr9 to both ends of the resistor string 4. In this specification, the term “voltage” simply refers to a potential from ground. The resistor string 4 has a voltage V provided by the constant voltage source 1.
This is a resistor string for equally dividing the voltage between r1 and the voltage Vr9 provided by the constant voltage source 2, and includes resistors 4a to 4a.
h. Note that the number of resistors included in the resistor array 4 is not limited to this. Here, the voltages Vr1 and Vr9
Are equally divided, but may not be equally divided.

The analog signal source 3 supplies the input voltage Vin to the A / D converter. The A / D converter receives the voltage Vin as an input signal and performs A / D conversion to output a digital value corresponding to the voltage Vin as an output signal.

The first amplifier circuit row 5 includes first amplifier circuits 6a to 6a.
6i. The first amplifier circuits 6a to 6i receive the input voltage V
After sampling in, difference voltages between the sampled voltage Vin and the reference voltages Vr1 to Vr9 are amplified and output.

The latch / intermediate holding circuit row 7 has first latch circuits 8a to 8i and intermediate holding circuits 9a to 9i. The first latch circuits 8a to 8i output digital signals by amplifying the output signals of the first amplifier circuits 6a to 6i, respectively. This digital signal is converted to a power supply voltage VDD (eg, 3.3 V) as an H (high) level.
Is set to the ground level VSS as the L (low) level.
(For example, 0 V). The intermediate holding circuits 9a to 9i
It receives and holds output signals of the first amplifier circuits 6a to 6i, respectively. In the first latch circuit 8, the input voltage Vin has eight voltage sections Vr1 to Vr2, Vr2 to Vr3, and Vr.
.., Vr8 to Vr9 to the upper data processing circuit 13.

The demultiplexer array 10 has demultiplexers 11a to 11i. Demultiplexer 11a
To 11i receive the outputs of the intermediate holding circuits 9a to 9i, respectively, and selectively output them to one of the signal lines si1 to si4.

The signal line array 12 has signal lines si1 to si4. The signal lines si1 to si4 are connected to the intermediate holding circuits 9a to 9a.
9i are respectively output to the second amplifier circuit 15
a to 15d.

The upper data processing circuit 13 includes a latch circuit 8
The digital signals output from a to 8i are received, encoded into higher digital values, and output. Here, the “higher digital value” is a value represented by the upper bits of the finally obtained digital value corresponding to the input signal. In this embodiment, the upper digital value has three bits of information because it represents one of the eight voltage intervals described above.

The upper data processing circuit 13 outputs a signal for controlling the operation to the demultiplexers 11a to 11i. Specifically, for example, when the input voltage is located between the voltages Vr3 and Vr4, for example, the voltage V
The upper data processing circuit 13 performs demultiplexing so that signals corresponding to r2, Vr3, Vr4 and Vr5 are output from the intermediate holding circuits 9b, 9c, 9d and 9e to the signal lines si1, si2, si3 and si4, respectively.
1a to 11i are controlled.

The second amplifier circuit row 14 includes a second amplifier circuit 15
a to 15d. The second amplifier circuits 15a to 15d are:
They are connected to the signal lines si1 to si4, respectively, and amplify and output signals output from four of the demultiplexers 11a to 11i.

The interpolation circuit 16 includes third amplifier circuits 17A1 to 17A1
17A4 and third amplifier circuits 17B1 to 17B3. The third amplifier circuits 17A1 to 17A4 are connected to the second
Amplify the voltage output from the amplifier circuits 15a to 15d,
Output. The third amplifier circuits 17B1 to 17B3 interpolate the output voltages of the adjacent second amplifier circuits 15a to 15d, respectively.

The second latch circuits 18a to 18g are connected to third amplifier circuits 17A1 to 17A4 and 17B1 to 17B1, respectively.
A digital signal is output by amplifying the output signal of 7B3. As in the operation of the first latch circuits 8a to 8i, this digital signal is set to the H level and the power supply voltage V
DD is set to L level to take the ground level VSS. For example, when the input voltage is located between, for example, the voltages Vr3 and Vr4, the interpolation circuit 16 outputs Vr2.
Between Vr3 and Vr3, between Vr3 and Vr4, and Vr
4 and Vr5. If the voltage of the input signal is between the voltages Vr2 and Vr3, the interpolation circuit 16 outputs +1 as the least significant bit (so-called carry bit) of the higher digital values. Conversely, the voltage of the input signal is Vr3 and Vr3.
If it is located between r4, the interpolation circuit 16 outputs -1 as the least significant bit (so-called carry bit) of the higher digital value. As will be described later, the interpolation circuit performs interpolation for finding the midpoint of the output voltage from the second amplification circuit 15. Therefore, the lower digital value has one bit of information except for the carry bit described above.

The clock generation circuit 19 synchronizes the operation of the entire circuit by outputting a clock to a latch circuit, a demultiplexer and the like. The lower data processing circuit 20 receives the digital signal output from the interpolation circuit 16 and converts the digital signal into a lower digital value. Arithmetic circuit 21
Receives the high-order data output from the high-order data processing circuit 13 and the low-order data output from the low-order data processing circuit 20, and performs a process of integrating the respective data to make a final (that is, all bits) data. A / D
Output the converted digital value. The clock input terminal 22 receives a clock having a frequency corresponding to the conversion frequency and outputs the clock to the clock generation circuit 19. Output terminal 23
Outputs the final A / D converted value.

The operation of the A / D converter according to the present invention will be described below with reference to a more detailed circuit diagram and FIG.

FIG. 9 is a circuit diagram of the first amplifier circuit 6.
Terminal a receives an analog signal having a voltage Vin.
The terminal b is connected to the reference voltage Vrn (n = 1,
2, 3, ..., 9) are received. Switches S1 to S3 are
By turning on / off at a timing described later, the operating state of the first amplifier circuit 6 is sampled and amplified by one of the following methods.
Set to one. Terminal c is connected to switches S1 to S3.
Receive a signal to control off. The signal sampled and amplified by the first amplifier circuit 6 is output from a terminal y. The sampling capacitor 24 performs sampling by charging to a voltage of an input analog signal. The inverting amplifier 25 amplifies and outputs the difference voltage between the analog signals input to the terminals a and b.

FIG. 10 shows ON / OFF of the switches S1 to S3 and the operation state of the first amplifier circuit 6 (sampling and amplification).
FIG. During the sampling period, the switch S
1 and S3 are on and switch S2 is off. Assuming that the capacitance value of the sampling capacitor 24 is C1, the charge Q1 stored in the sampling capacitor 24 is expressed by the following equation.

Q1 = C1 · (Vin−Va) (Equation 4) Here, the voltage Vin is the instantaneous value of the analog signal voltage input to the terminal a when the switch S1 changes from on to off (see FIG. 10). (An instantaneous value of the analog signal at time t1). The voltage Va is a voltage at the input terminal (that is, the terminal B) and the output terminal of the inverting amplifier 25 when the switch S3 is on.

In the amplification state, switches S1 and S3 are off, and switch S2 is on. At this time, the reference voltage Vrn (n = 1, 2, 3,.
.. 9) are given. When the switch S3 is off, the terminal B is in an open state (open state), and the charge Q1 of the capacitor 24 accumulated during the sampling period is held. Therefore, the following equation holds for the voltage VB of the terminal B.

Q1 = C1 · (Vrn−VB) (Equation 5) When the Q1 is erased from the equations 4 and 5, and the voltage VB is rearranged, the following equation is obtained.

VB = Vrn−Vin + Va (Equation 6) As can be seen from Equation 6, in the amplification state, the voltage VB
Is shifted by a voltage (Vrn−Vin) from the voltage Va at the terminal B when the switch S3 is on.

The inverting amplifier 25 has an input voltage V
When it is near a, it is assumed that it has a voltage gain (-G) (G >> 0). At this time, the output voltage Vo1 of the first amplifier circuit 6
Is represented by the following equation.

Vo1 = −G · (Vrn−Vin) + Va (Formula 7) As expressed by the above formula, the output voltage Vo of the first amplifier circuit 6
In 1, the voltage difference between the voltage Vin of the analog signal and the reference voltage Vrn is amplified by the gain (−G) and shifted by the voltage Va.

FIG. 11 is a circuit diagram of the first latch circuit 8 and the second latch circuit 18. Since the first latch circuit 8 and the second latch circuit 18 have the same configuration, only the first latch circuit 8 will be described below. The second latch circuit 18 functions similarly to the first latch circuit 8. In the following description, reference numerals in parentheses immediately after reference numerals of the first latch circuit 8 represent corresponding terminals of the second latch circuit 18.

The terminal d (terminal p) receives the signal output from the output terminal y of the first amplifier circuit 6. Inverting amplifier 2
The input terminal 7 receives the signal output from the output terminal of the inverting amplifier 26. That is, the inverting amplifiers 26 and 27
Form a non-inverting amplifier by being connected in series. The signal amplified by inverting amplifiers 26 and 27 connected in series is output from terminal f (terminal r). The switches S4 and S5 are turned on / off at timings described later, thereby setting the operation states of the first latch circuit 8 and the second latch circuit 18 to one of latch and through. Terminal e (terminal q) receives a signal for controlling on / off of switches S4 and S5.

FIG. 12 shows the on / off states of the switches S4 and S5, the first latch circuit 8 and the second latch circuit 18,
FIG. 5 is a diagram showing an operation state (latch and through) of FIG.
During the latch period, the switch S4 is off and the switch S5 is on. At this time, the input terminal of the non-inverting amplifier constituted by the inverting amplifiers 26 and 27 (that is, the input terminal of the inverting amplifier 26) is connected to the output terminal (that is, the output terminal of the inverting amplifier 27). The input terminal of the non-inverting amplifier is disconnected from the terminal d. As a result, the input digital value is held by the latch circuit 8.

In the through period, the switch S4 is on and the switch S5 is off. At this time, the inverting amplifier 26 receives the signal input from the terminal d, amplifies the signal, and outputs the amplified signal to the inverting amplifier 27. Further, the inverting amplifier 27 amplifies the signal output from the inverting amplifier 26 and outputs the amplified signal at the terminal f. The signal input to the terminal d is converted into a digital signal by being amplified by the inverting amplifiers 26 and 27. This digital signal takes the power supply voltage VDD as the H level and the ground level VSS as the L level.

FIG. 13 is a circuit diagram of the intermediate holding circuit 9. The terminal A receives a signal from the output terminal y of the first amplifier circuit 6. The holding capacitor 28 holds the voltage of the signal input to the terminal A. The switch S6 is turned on / off at a timing described later to set the operation state of the intermediate holding circuit 9 to one of charging and transferring. The terminal B receives a signal for controlling on / off of the switch S6. The terminal D outputs a signal having the held voltage.

FIG. 14 shows ON / OFF of the switch S6,
FIG. 3 is a diagram illustrating an operation state (charging and transfer) of an intermediate holding circuit 9; During the charging period, the switch S6 is on. During the charging period, the holding capacitor 28 holds the voltage of the signal output from the first amplifier circuit 6. In the transfer period, a charge corresponding to the held voltage is transferred to the second amplifier circuit 15. This charge transfer will be described later in detail.

FIG. 15 is a circuit diagram of the demultiplexer 11. Terminal g receives the signal output from intermediate holding circuit 9. When one of the switches S7 to S10 is exclusively turned on, the input signal is selectively output to the terminals i1 to i4. The terminal h receives a signal for controlling on / off of the switches S7 to S10.

FIG. 16 shows that the switches S7 to S10 are turned on.
OFF and the conduction state of the demultiplexer 11 (i1 to i
4). When the switches S7 to S10 are on, the terminal g is connected to the terminals i1 to i4, respectively. Terminals i1 to i of demultiplexers 11a to 11i
4 are connected to the signal lines si1 to si4, respectively.

FIG. 17 is a circuit diagram of the second amplifier circuit 15. Terminals j of the second amplifier circuits 15a to 15d are connected to signal lines si1 to si4, respectively. Inverting amplifier 2
9 receives an output from the demultiplexer 11 at a terminal j via a signal line array 12. The feedback capacitor 30 is connected to an input terminal and an output terminal of the inverting amplifier 29. The switch S11 is connected to two terminals of the feedback capacitor 30. When discharging the charge stored in the feedback capacitance 30, the feedback capacitance 30 is turned on. Terminal k
Receives a signal for controlling on / off of the switch S11. The terminal 1 outputs a signal from the output terminal of the inverting amplifier 29.

FIG. 18 is a diagram showing ON / OFF of the switch S11 and an operation state (reset and sampling) of the second amplifier circuit 15. When the switch S11 is ON, the feedback capacitor 30 is short-circuited, so that the second amplifier circuit 1
5 is in a reset state. That is, in the reset state, the voltage Va when the input terminal and the output terminal of the inverting amplifier 29 are short-circuited is output from the terminal l. When the switch S11 is off, the charge corresponding to the input voltage is stored in the feedback capacitor 30, and sampling is performed.

The operations of the first amplifier circuit 6, the intermediate holding circuit 9, the demultiplexer 11, the signal line array 12, and the second amplifier circuit 15 in the A / D converter of the present invention are expressed by the following equations (7) to (3).
This will be described in detail below with reference to FIGS. FIG. 19 is a circuit diagram showing elements representing the first amplifier circuit 6, the intermediate holding circuit 9, the demultiplexer 11, the signal line array 12, and the second amplifier circuit 15 in FIG. FIG. 22 is a diagram showing the timing of the operation performed by the elements of the circuit shown in FIG. In FIG. 22, the operation is performed in order from left to right as time elapses.

In FIG. 19, when the first amplifier circuit 6 is in the amplification state, the output voltage Vo1 at the terminal A of the first amplifier circuit 6 is Vo1 = −G ·
(Vrn−Vin) + Va (Equation 7) When the first amplifier circuit 6 amplifies, the intermediate holding circuit 9 is in a charged state (see FIG. 22), and the switch S6 is on.
The holding capacitor 28 of the intermediate holding circuit 9 charges the output voltage Vo1 of the first amplifier circuit 6. The capacitance value of the storage capacitor 28 is C2
Then, the charge Q2 stored in the storage capacitor 28 is expressed by the following equation.

Q2 = C2 · (−G · (Vrn−Vin) + Va) (Equation 8) By expanding a part of Equation 8, Q2 = C2 · (−G · (Vrn−Vin)) + C2 · Va ( (Equation 9) If the first and second terms on the right side of Equation 9 are Q2a and Q2b, respectively, Q2a = C2 · (−G · (Vrn−Vin)) (Equation 10) Q2b = C2 · Va (Equation 11) When the switch S7 of the demultiplexer 11 is on and the switches S8, S9, and S10 are off, the terminal g of the demultiplexer 11 is connected to the signal line si1 of the signal line array 12. At this time, the switch S6 of the intermediate holding circuit 9 is off. As shown in FIG. 8, signal lines si1, si2, si3, and si4 each have 9 lines.
Demultiplexers are connected. As a result, there is a parasitic capacitance that cannot be ignored at the point where the switches S7 to S10 are connected to the signal lines si1 to si4. In FIG. 19, this parasitic capacitance is
1 is represented as a capacitor CS connected to the capacitor C1.

The second amplifier circuit 15 receives the charge Q2a stored in the storage capacitor 28 of the intermediate storage circuit 9. The second amplifier circuit 15 resets (the switch S11 is on) before performing sampling (the switch S11 is off), which is the operation of receiving the charge Q2a. During this reset period, the switches S7 to S10 of the demultiplexer 11 are in a standby period in which all the switches are off. Therefore, during the reset period, the voltage of the terminal j is set to the switch S1
It is equal to the voltage Va output when 1 is on. Therefore, the charge QS stored in the parasitic capacitance CS during the reset period
r is represented by the following equation.

QSr = CS · Va (Equation 12) Since the switch S11 is on during the reset period, the charge Q3r charged in the capacitor 30 (capacitance value C3) is zero.

Q3r = 0 (Equation 13) During the sampling period of the second amplifier circuit 15, the switch S7 of the demultiplexer 11 is on, the switch S6 of the intermediate holding circuit 9, the switch S11 of the second amplifier circuit 15, and the switch S7. The switches S8 to S10 of the multiplexer are off. As a result, the charge Q2a stored in the storage capacitor 28 of the intermediate storage circuit 9 is transferred to the second amplification circuit 15. The step of transferring the charges will be described below using mathematical expressions. The voltage at the terminal j during the sampling period is (Vj + V
a), the output voltage Vo2 of the second amplifier circuit 15 is
It is expressed by the following equation.

Vo2 = −G · Vj + Va (Equation 14) where (−G) (G >> 0) is the voltage gain of the inverting amplifier 29 of the second amplifier circuit 15. The voltage difference Vjl between the terminal j and the terminal l is represented by the following equation.

Vjl = (Vj + Va) −Vo2 (Equation 15) By substituting Equation 14 into Equation 15, Vjl = (1 + G) · Vj (Equation 16) The electric charge Q3h stored in the capacitor 30 having the capacitance value C3 becomes
It is expressed as the following equation.

Q3h = C3 · Vjl (Expression 17) By substituting Expression 16 into Expression 17, Expression 18 is obtained.

Q3h = C3 · (1 + G) · Vj (Equation 18) Charge Q2h stored in the storage capacitor 28 having the capacitance value C2
Is represented by the following equation.

Q2h = C2 · (Vj + Va) (Equation 19) The charge QSh stored in the parasitic capacitance CS is expressed by the following equation.

QSh = CS · (Vj + Va) (Equation 20) In the reset period and the sampling period, the charge amounts stored in the capacitors C2, CS, and C3 are preserved, so the following expression holds.

Q2 + QSr + Q3r = Q2h + QSh + Q3h (Equation 21) Substituting Equations 9, 12, 13, 18, 19 and 20 into Equation 21 and rearranging the voltage Vj at the terminal j gives the following equation.

[0094]

(Equation 1)

By dividing the numerator of Equation 1 and the denominator by G, the following equation is obtained.

[0096]

(Equation 2)

Here, considering the actual design value, the following equation is established.

C2, C3, CS << G (Equation 22) When Equation 22 is applied to Equation 2, Equation 1 is easily understood.
Can be transformed into

Vj = −C2 / C3 · (Vrn−Vin) (Expression 23) That is, the voltage change expressed by Expression 23 is transmitted to the terminal j in FIG. The transmitted signal is a voltage obtained by multiplying the voltage difference between the reference voltage Vrn and the analog signal Vin by (−C2 / C3), and the voltage to be A / D converted (Vrn−V)
in) is transmitted. Equation 23
Means that the transmitted voltage Vj is not affected by the parasitic capacitance CS. This is because the negative feedback operation of the inverting amplifier 29 by the feedback capacitor 30 suppresses the voltage change at the terminal j in FIG. 19, and as a result, the charge and discharge of the charge to the parasitic capacitor CS is hardly performed. Therefore, the second amplifier circuit 15 can operate without being affected by the parasitic capacitance CS. This is a great effect that the signal transmission circuit, the signal transmission method, and the A / D converter according to the present invention have over the prior art. As you can see from the above explanation,
According to the present invention, even if the parasitic capacitance CS having a large value exists on the signal lines si1 to si4, signal transmission can be performed efficiently, and as a result, high-speed operation of the circuit can be realized. Terminal l
Is given by the following equation.

Vo2 = −G · Vj + Va (Expression 24) By substituting Expression 23 into Expression 24, the following expression is obtained.

Vo2 = G · C2 / C3 · (Vrn−Vin) + Va (Formula 25) FIG. 20 is a circuit diagram of the third amplifier circuits 17A and 17B. FIG. 20 shows only the third amplifier circuits 17A1, 17A2 and 17B1, but the third amplifier circuits 17A3, 17A
The blocks A4, 17B2 and 17B3 have the same configuration.

The sampling capacitors 31 and 36 sample the voltages input at the terminals m and E, respectively. The interpolation capacitors 33 and 34 are connected in series, and their capacitance values are equal. Therefore, the voltage at the point where the interpolation capacitors 33 and 34 are connected is equal to the average voltage of the voltage of the terminal m and the voltage of the terminal E. Inverting amplifiers 32, 35 and 37
Respectively receives and amplifies the voltage of the terminal m, the average voltage of the terminal m and the terminal E, and the voltage of the terminal E, and outputs the amplified voltages from the terminals o, F and G. Switch S12
14 sets the input terminals and the output terminals of the inverting amplifiers 32, 35 and 37 to short-circuit or open-circuit, respectively.
The terminal m is connected to the output terminal 1 of the second amplifier circuit 15, and the terminal E is connected to the second amplifier circuit 15 connected to the terminal m.
Is connected to the output terminal 1 of the second amplifier circuit 15 adjacent to. The terminal n receives a signal for controlling on / off of the switches S12 to S14.

FIG. 21 is a diagram showing ON / OFF of the switches S12 to S14 and the operating states (sampling and amplification) of the third amplifier circuits 17A and 17B. Switch S1
When S2 to S14 are on, the third amplifier circuits 17A and 17B sample the input signals. Switch S
When 12 to S14 are off, the third amplifier circuits 17A and 17B compare the voltage of the input signal with the voltage sampled during the sampling period. The third amplifier circuit 17 is described below.
The operation of A and 17B will be described in detail.

Referring again to FIG. 22, the third amplifier circuit 1
In the reset period of 7A and 17B (shown as a sampling period in FIG. 21), the second amplification circuit 15
Is also the reset period. The voltage input to the terminals m and E is the output voltage Va when the switch S11 of the second amplifier circuit 15 is on. Next, when the voltages input to the terminals m and E in the amplification states of the third amplifier circuits 17A and 17B are voltages Vo2m and Vo2E, respectively, the following equations are obtained.

Vo2m = G · C2 / C3 · (Vrn−Vin) + Va (Equation 26) Vo2E = G · C2 / C3 · (Vr (n + 1) −Vin) + Va (Equation 27) Here, the voltages Vrn and Vr ( (n + 1) is a reference voltage from the adjacent resistor string 4. Voltages Vo2m and V
o2E corresponds to the reference voltage in the first amplifier circuit 6. Therefore, the output voltage Vo3o of the third amplifier circuit 17A1 and the output voltage Vo3G of the third amplifier circuit 17A2 are expressed by the following equation (7).
, The following equation is obtained.

Vo1 = −G · (Vrn−Vin) + Va (Formula 7) Vo3o = −G · (Vo2m−Va) + Va (Formula 28) Vo3G = −G · (Vo2E−Va) + Va (Formula 29) Formula 26 By substituting Equation 27 and Equation 27, the following equation is obtained.

Vo3o = −G · G · C2 / C3 · (Vrn−Vin) + Va (Equation 30) Vo3G = −G · G · C2 / C3 · (Vr (n + 1) −Vin) + Va (Equation 31) Capacity 33 And the capacitance of the capacitor 34 are equal, so that the terminal F
Is equal to an intermediate value between the voltage of the terminal o and the voltage of the terminal G. Therefore, the output voltage Vo3F at the terminal F is expressed by the following equation.

Vo3F = (Vo3o + Vo3G) / 2 (Expression 32) By substituting Expressions 30 and 31, the following expression is obtained.

Vo3F = −G · G · C2 / C3 · ((Vrn + Vr (n + 1)) / 2−Vin) + Va (Equation 33) When Expression 33 is compared with Expressions 30 and 31, the circuit shown in FIG. For example, adjacent reference voltages Vrn and Vr (n +
1) intermediate reference voltage ((Vrn + Vr (n + 1)) /
Since 2) can be obtained, the data of A / D conversion (that is, the resolution of A / D conversion) can be increased. Voltage Vo3 output from third amplifier circuits 17A and 17B
o, Vo3G and Vo3F are connected to the second latch circuit 18
(See FIG. 8 and FIG. 11). The digital value output from the second latch circuit 18 is encoded into a lower digital value by the lower data processing circuit 20 (see FIG. 8).

In the present embodiment, the lower data processing circuit 20 outputs +1, 0 and −1 to the arithmetic circuit 21 as carry bits. Thereby, for example, the voltage Vin
Is slightly larger than the voltage Vr3 (where Vr1> V
r9), an erroneous result that the voltage Vin is located between the voltages Vr3 and Vr4 indicates that the upper data processing circuit 1
3, the error can be corrected by the carry bit. The arithmetic circuit 21 outputs a final digital value having all bits converted based on the upper digital value, the lower digital value, and the carry bit (here, the upper 3 bits and the lower 1 bit in total, 4 bits). 23. The clock generation circuit 19 supplies a clock signal supplied to each circuit block described above.

Referring back to FIG. Assuming that the operations shown in the timing chart of FIG. 22 are executed in a time corresponding to one clock cycle (hereinafter referred to as one clock period), the conversion cycle is equal to two clock periods.
That is, only two clock periods are required to convert an analog signal input at a certain time into a digital signal. This is because, according to the A / D converter of the present invention, the first
Amplifying circuit 6, first latch circuit 8, high-order data processing circuit 1
3. The intermediate holding circuit 9, the demultiplexer 11, the second amplifier circuit 15, the third amplifier circuits 17A and 17B, the second latch circuit 18, and the lower data processing circuit 20 perform pipeline processing in two clock periods. It depends on what you do. As a result, according to the present invention, with low power consumption,
In addition, high-speed A / D conversion can be performed.

The first amplifier circuit 6 performs sampling and amplification.
During the clock period, a voltage corresponding to the difference between the reference voltage and the input voltage is output. The first latch circuit 8 controls the first amplifier circuit 6 in two clock periods of through and latch.
Is converted into a digital value and output to the upper data processing circuit 13. Upper data processing circuit 13
Is based on the digital value from the first latch circuit 8,
The demultiplexer 11 is controlled such that signals corresponding to the four reference voltages near the input voltage Vin are output from the intermediate holding circuit 9 to the signal lines si1 to si4. For example, if the voltage Vin is located between the voltage Vr3 and the voltage Vr4, the demultiplexer 11 is controlled so that the output from the intermediate holding circuits 9b to 9e is selectively supplied to the signal lines si1 to si4. The high-order digital value output by the high-order data processing circuit 13 is combined with the low-order digital value output by the low-order data processing circuit 20 which is output after one clock period, to become a final digital value having all bits.

First, the intermediate holding circuit 9 charges the output from the first amplifier circuit 6. Next, during the clock period in which the first latch circuit 8 is in the latch state, the charge is transferred to the second amplifier circuit 15 via the demultiplexer 11. The second amplifier circuit 15 receives and samples the voltage output from the intermediate holding circuit 9 during the clock period when the demultiplexer 11 is in the selected state. Third amplifier circuits 17A and 17B
Receives and amplifies the sampled voltage. The second latch circuit 18 converts the voltage amplified by the third amplifier circuits 17A and 17B into a digital value, and outputs the digital value to the lower data processing circuit 20 in the latch state. The lower-order data processing circuit 20 obtains a higher-order digital value from the upper-order data processing circuit 13 and a lower-order digital value from the lower-order data processing circuit 20 during the operation clock period, and thus calculates the final digital value having all bits. can do. As can be seen from FIG. 22, the time lag between the input analog signal and the output digital signal is 5 clock periods, but the operation of each circuit element is completed in 2 clock periods.

In the embodiments described above,
Although the upper digital value has 3-bit information and the lower digital value has 1-bit information, the present invention is not limited to this.

(Embodiment 3) The result of comparing the signal transmission circuit of the present invention with the signal transmission circuit of the prior art by simulation will be described below.

FIG. 24 is a circuit diagram of the signal transmission circuit of the present invention. The drive circuit 242 receives a signal from the input signal source 241, amplifies the signal, and outputs the amplified signal to one terminal of the switch 248. In the holding state, the switches 248 and 2414 are on and the switch 249 is off, so that the capacitor C0 holds the charge corresponding to the output of the input signal source 241. When in transfer state, switch 2
49 is on, switch 248 and switch 24
14 is off, and the charge held in the capacitor C0 is transferred to the input terminal of the inverter 2416 via the signal line 243. The input terminal and the output terminal of the inverter 2416 include a switch 2414 and a feedback capacitor 24.
15 is connected, and amplifies the signal given to the input terminal and outputs the amplified signal to the driven circuit 244. At this time, an equivalent capacitance substantially equal to a value obtained by multiplying the capacitance Cf of the feedback capacitance 2415 by the gain of the inverter 2416 is regarded as being connected between the input terminal of the inverter 2416 and the ground.

FIG. 25 is a diagram showing operation timings of switches 248, 249 and 2414 in the signal transmission circuit shown in FIG. 24, and changes in input voltage of driven circuit 244. In the period of holding 1, the switch 2414 is in an on state, and the input / output terminal of the inverter 2416 is fixed at the same voltage value Va. At this time, the feedback capacity 2415
Does not accumulate charge.

Next, in the period of transfer 1, the switch 24
14 changes to the off state. At this time, the storage capacity 2410
The charge is distributed to the capacitor C1 and the feedback capacitor 2415 via the switch 249 according to the accumulated charge amount.
When the absolute value | A | of the gain of inverter 2416 is much larger than 1, the value of capacitance C1 of signal line 243 is not dominant, and the difference between the output voltage of inverter 2416 and voltage Va is the difference between capacitance C0 and voltage Va. It becomes possible to control by the ratio of Cf.

As described above, in the signal transmission circuit of FIG. 24, it is possible to amplify the difference voltage between the input voltage input to driven circuit 244 and the reference voltage. The amplification degree can be controlled by arbitrarily setting the capacitance ratio between the capacitance C0 and the feedback capacitance 2415.

FIG. 26 is a diagram showing the output voltage waveform of the signal transmission circuit of the present invention shown in FIG. 24 and the output voltage waveform of the conventional signal transmission circuit shown in FIG. Both waveforms are obtained by simulation. FIG.
FIG. 3 is a diagram illustrating a configuration of a signal transmission circuit according to a conventional technique. The drive circuit 272 receives and amplifies the output from the input signal source 271 and outputs the amplified signal to one terminal of the selection switch 276. The driven circuit 274 receives a signal via a signal line 273 connected to the selection switch 276. Signal line 27
Parasitic capacitance 2718 exists between 3 and ground.

FIG. 28 is a diagram showing the selection state of the selection switch of the conventional signal transmission circuit of FIG. 27 and the input voltage of the driven circuit 274, and the horizontal axis shows time. In FIG. 28, in the selection state 2 in which the selection switch 276 is on, the input voltage of the driven circuit 274 changes from the voltage V1 to the voltage V2.
To ΔV. When the switch 276 is turned off in the selection state 3, the input voltage of the driven circuit 274 converges to the voltage V3.

Table 1 shows the current consumption and settling time of the present invention obtained by simulation in comparison with those of the prior art.

[0123]

[Table 1]

When the current consumption of the signal transmission circuit according to the present invention is substantially equal to that of the signal transmission circuit according to the prior art, the signal transmission circuit according to the present invention has a settling time which is about １ ／ that of the circuit according to the prior art. Be shortened.

In the present embodiment, the configuration of inverter 2416 and the capacitance of feedback capacitor 2415 are arbitrary. Further, the switch 248 in the present embodiment,
The operation timings of 249 and 2414 can be operated at arbitrary timings as long as the operation of the signal transmission circuit is not impaired.

(Embodiment 4) FIG. 29 is a circuit diagram of a solid-state imaging device using a signal transmission circuit according to the present invention. FIG.
In 9, 291 is a diode (so-called photodiode) for converting light into electric charges, 292 and 295 are parasitic diodes, and 293 is a switch. The anode (anode) of the diode 291 is connected to one terminal of the switch 293, and the negative electrode (cathode) is connected to the node A. The other terminal of the switch 293 has a constant voltage V
a. The anode (anode) of the parasitic diode 295 is connected to the constant voltage A, and the negative electrode (cathode) is connected to the node A. Image element 29 for detecting light by switch 293 and diodes 291 and 292
4. In the configuration example of FIG.
91 and the switch 293, the parasitic diode 2
The configuration obtained by adding 92 is defined as an image element 294, and the parasitic diode 295 is also considered between the node A and the constant voltage A. Considering these parasitic diodes, the image element 294
Is formed when MOS transistors are used.

The diode 291 in FIG. 29 includes a junction capacitance due to reverse bias as a parasitic capacitance, which corresponds to C0 in FIG. The capacitance of the wiring connected to the node A and the parasitic capacitance of the diode 295 correspond to the capacitance C1 in FIG. Inverter 296, switch 297, and capacitor 298 correspond to inverter 202, switch 206, and capacitor 204 in FIG. 5, respectively. Therefore, the relationship C0 << (C1 + C2) described with reference to FIG.
The fact that it is preferable that C1 <C2 also holds true in the present embodiment. In the present embodiment, an inverter 296 having a capacitor 298 connected to its input terminal and output terminal is used. Alternatively, a variable capacitor shown in FIG. 6 may be used.

The output terminals 292 of the five image elements 294 are connected to the common (node A) and are connected to the input terminal of the inverter 296. The output terminals 292 of the five image elements 294 are also connected to the constant voltage A in common. The switches 293 of the five image elements 294 are controlled to open and close by output signals L1 to L5 of the scanning circuit 299. The switch 297 connected between the input and output terminals of the inverter 296 is controlled to open and close by the output signal L0 of the scanning circuit 299. The five image elements 294 are referred to as a first row image element group 29G1 arranged in a plane. The second and third row image element groups 29G2 and 29G3 have the same configuration as the first row image element group 29G1, and a detailed description thereof will be omitted.

The image formed by the optical lens is converted into an electric signal by reading out the electric charge stored in each image element 294 arranged in rows and columns. The image is converted into an electrical signal corresponding to each image element 294. In other words,
Diode 2 for detecting light constituting each image element 294
The voltage conversion of the electric charge accumulated in 91 can realize conversion of an image into an electric signal.

The following is a description of the operation. The opening and closing operation of the switch 293 of each image element 294 and the opening and closing of the switch 297 connected between the input and output terminals of the inverter 296 are controlled by the scanning circuit 299. FIG.
9 is a timing chart showing a control procedure of the scanning circuit 299. The control procedure will be described below with reference to FIG.

The basic clock is input to the input terminal 2910 of the scanning circuit 299.
At 99, the scan clocks L0 to L5 are output. The clock signal L0 is a control signal for the switch 297, and the clock signals L1 to L5 are control signals for the switches 293 forming each image element arranged in a row. When the clock signal L0 that controls the switch 297 is at a high level,
N), and indicates an open state (OFF) when at the low level. The clock signals L1 to L5 are in a closed state (ON) when at a low level, and are in an open state (OFF) when at a high level.

In the first period, the image elements 294 in the first column
The purpose is to initialize the amount of charge accumulated in the diode 291 that detects the light constituting. During this period, the switch 297 is closed, the input terminal and the output terminal of the inverting amplifier circuit are short-circuited, and the output terminal of the inverting amplifier circuit outputs the bias voltage Vb.

The clock signal L1 is supplied to the switch 29 in the first column.
3, the diode 291 is connected to the constant voltage Va. Here, the constant voltage Va is a voltage lower than the bias voltage Vb, and is a voltage lower than the bias voltage Vb.
Assume that 2 and 295 can be sufficiently biased in the reverse direction. Since the diode 291 is biased in the reverse direction, a depletion layer develops at the pn junction. Since the depletion layer has low electric conductivity, the depletion layer functions as a capacitance between the p region and the n region. This capacitance is called a depletion layer capacitance. The depletion layer capacitance is determined by switch 29
When 3 is in the closed state, it becomes a value Cd1 determined by the voltage difference between the constant voltage Va and the bias voltage Vb, and the charge amount stored in the depletion layer capacitance is Q1 = Cd1 · (Vb−Va).

In the second to ninth periods, the purpose of the diode 291 constituting the image element in the first column is to convert light energy into a charge amount and store the charge amount. During this period, the clock signal L1 causes the switches 293 forming the image elements in the first column to be in an open state. At this time, the energy of light (hν: h is Planck's constant, ν is the frequency of light) excites electrons bound to nuclei existing in a depletion layer on the pn junction surface of the diode 291. The number of excited electrons increases with an increase in light energy (hv). The excitation phenomenon causes holes to be generated in the depletion layer in the p region and electrons to be generated in the depletion layer in the n region. Holes are accumulated in the p region and electrons are accumulated in the n region. This is a charge generated by light energy (hν), and the amount of this charge is defined as Δq. At this point,
The charge amount stored in the depletion layer capacitance is (Q1 + Δq).

In the tenth period, the object is to transfer the amount of electric charge Δq accumulated in the diode 291 constituting the image element of the first column to the capacitor 298 connected to the input / output terminal of the inverter 296 and to output it as a voltage. And During this period, the switch 297 is open and the switch 293 is closed, and the anode of the diode 291 is connected to the constant voltage Va. Due to the negative feedback operation of the inverter 296, the terminal A
Means that the switch 297 is open but the bias voltage V
There is almost no change from b. The voltage applied to the diode 291 by the negative feedback operation of the inverter 296 becomes substantially (Vb-Va), the value of the depletion layer capacitance becomes Cd1, and the accumulated charge returns to Q1. As a result, the electric charge Δq accumulated by the light energy (hν) in the previous period (second to ninth periods) moves to the capacitor 298.

Here, during the second to ninth periods, the depletion layer in the parasitic diode 292 is shielded and does not enter light, so that no new charge is generated in this depletion layer. Further, the depletion layer in the parasitic diode 295 is also shielded, and no new charge is generated by light. In addition, since the voltage difference between both ends of the parasitic diode 295 hardly changes, the existing charges hardly move to the capacitor 298.

Therefore, in this tenth period, only the electric charge Δq accumulated in the diode 291 is transferred to the capacitor 298. The transferred charge Δq is converted into a voltage Vo = Δq / C2 (provided that the voltage gain of the inverter 296 is sufficiently large) by the capacitance value C2 of the capacitor 298, and is output to the output terminals 2911 to 2913, respectively.

In the above description, after the charges accumulated in the image elements in the first column are initialized, the energy of light incident on the depletion layer region is converted into charges, and then the charges converted into the capacitance of the inverter 296 are transferred. A series of operations for outputting the voltage as a voltage has been described for the first to tenth periods. The remaining second to fifth columns perform the same operation as that of the first column with a half cycle of the basic clock. In this way, the charges accumulated in each image element are sequentially converted into voltage signals.

The solid-state imaging device 2914 can be applied to a device for converting an image into a radio wave and displaying the image on a remote image display device. FIG. 31 is a block diagram showing a configuration of a device to which the solid-state imaging device 2914 of FIG. 29 is applied. The device in FIG. 31 includes a transmitting unit that transmits an image as a radio wave, and a receiving unit that receives the radio wave and projects the image. The components depicted in FIGS. 29 and 31 having the same reference numerals correspond to one another. In the transmission unit, reference numeral 3115 denotes a clock generation circuit that supplies a clock signal required for each component. Reference numeral 3116 denotes output terminals 2911 to 2911 of the image sensor 2914.
2913 continuous electrical signals (so-called analog signals)
Is an A / D converter that converts a digital signal into a discrete electric signal (so-called digital signal). 3117 is an A / D converter 311
6 is a signal processing circuit for converting the digital signal converted by 6 into a form easy to transmit as a radio wave, and 3118 is a transmission circuit 3118 for converting the output signal of the signal processing circuit 3117 into a radio wave.

In the receiving section, reference numeral 3120 denotes a clock generating circuit for supplying a necessary clock signal to each component of the receiving section. Reference numeral 3119 denotes a receiving circuit that receives a radio wave transmitted from the transmitting circuit 3118 of the transmitting unit. Reference numeral 3121 denotes a signal processing circuit that performs digital signal processing on a signal from the receiving circuit. Reference numeral 3122 denotes a D / A conversion circuit for converting a digital output signal of the signal processing circuit 3121 into an analog electric signal. Reference numeral 3123 denotes a liquid crystal display that controls the reflectivity by changing the crystal structure in accordance with an analog electric signal, and displays an image to be seen by a human.

The solid-state imaging device 2914 of the transmission section outputs the analog electric signal converted by the imaging device to the terminals 2911 to 2913 for each column. Terminals 2911-29
The 13 analog electric signals are provided by A /
The data is converted into a digital signal by the D converter 3116 to become image data. The signal processing circuit 3117 receives the converted digital signal, and converts the converted digital signal into serial data suitable for transmission by digital signal processing of image data.
The transmission circuit 3118 modulates the converted serial data and transmits it in the form of a radio wave.

The receiving circuit 3119 of the receiving unit receives the radio wave, amplifies the received signal to obtain a required voltage, and performs waveform shaping. The signal processing circuit 3121 includes a receiving circuit 3119
Receiving the digital output signal output from the device, and removing noise and distortion received during signal transmission in the form of radio waves using digital signal processing. D / A converter 3122
Receives a digital signal output from the signal processing circuit 3121, converts the digital signal into an analog electric signal, and drives the liquid crystal display 3123 to reproduce an image taken by the image sensor 2914.

In particular, in the transmitting section, the image pickup device 291
4. Clock generation circuit 3115, A / D converter 3116
Since the signal processing circuit 3117 can be formed by a CMOS process, circuits other than the transmission circuit 3118 can be manufactured by one chip. Further C
As the miniaturization of the MOS process progresses, a transmission circuit 3118 including a high-frequency circuit can be integrated.

According to the fourth embodiment, the same effects as those of the A / D converter and the signal transmission circuit and signal transmission method described above can be obtained. That is, even when the driving force of the input signal source is small and the parasitic capacitance of the signal line to be driven is large, high-speed and high-efficiency signal transmission can be performed.

[0145]

According to the signal transmission circuit and the signal transmission method of the present invention, an analog signal can be transmitted at a high speed with a small driving capability through a signal line having a large parasitic capacitance. Further, according to the A / D converter of the present invention, an analog signal can be converted into a digital signal by using an amplifier circuit having a small driving capability. As a result, the power consumption of the A / D converter can be reduced, and the chip area of the semiconductor chip of the integrated A / D converter can be reduced. According to the A / D converter of the present invention, the D / A
Since it is not necessary to use a converter, power consumption can be reduced and the chip size can be reduced. According to the solid-state imaging device of the present invention, the A / D of the above-described present invention is used.
An effect similar to that of the converter can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of a signal transmission circuit and a signal transmission method according to the present invention.

FIG. 1 is a diagram when (C1 + C2) >> C0 is satisfied;
3 is an equivalent circuit diagram of the circuit of FIG.

FIG. 3 is a circuit diagram illustrating an example of a charge supply unit that supplies a charge Q0 to a capacitor C0.

FIG. 4 is a circuit diagram showing a charge supply unit using a diode.

FIG. 5 is a circuit diagram showing an example of a conversion unit 200.

FIG. 6 is a circuit diagram of a conversion unit 200 using a variable capacitor.

FIG. 7 is a block diagram of an A / D converter according to the present invention.

FIG. 8 is a circuit diagram of an A / D converter according to the present invention.

FIG. 9 is a circuit diagram of the first amplifier circuit 6.

FIG. 10 is a diagram showing ON / OFF of switches S1 to S3 and an operation state (sampling and amplification) of a first amplifier circuit 6.

FIG. 11 shows a first latch circuit 8 and a second latch circuit 18.
FIG.

FIG. 12 is a diagram showing ON / OFF of switches S4 and S5 and operation states (latch and through) of a first latch circuit 8 and a second latch circuit 18.

FIG. 13 is a circuit diagram of the intermediate holding circuit 9;

FIG. 14 is a diagram showing ON / OFF of a switch S6 and an operation state (charging and transfer) of an intermediate holding circuit 9;

FIG. 15 is a circuit diagram of the demultiplexer 11;

FIG. 16 is a diagram showing ON / OFF of switches S7 to S10 and conduction states (i1 to i4) of demultiplexer 11;

FIG. 17 is a circuit diagram of the second amplifier circuit 15.

FIG. 18 is a diagram showing ON / OFF of a switch S11 and an operation state (reset and sampling) of a second amplifier circuit 15.

FIG. 19 is a circuit diagram showing elements representing the first amplifier circuit 6, the intermediate holding circuit 9, the demultiplexer 11, the signal line array, and the second amplifier circuit 15 in the A / D converter of FIG.

FIG. 20 is a circuit diagram of third amplifier circuits 17A and 17B.

FIG. 21 is a diagram showing ON / OFF of switches S12 to S14 and operation states (sampling and amplification) of third amplifier circuits 17A and 17B.

FIG. 22 is a diagram illustrating timings of operations performed by elements of the circuit illustrated in FIG. 8;

FIG. 23 is a block diagram showing a serial-parallel A / D converter according to the related art.

FIG. 24 is a circuit diagram of a signal transmission circuit of the present invention.

25 is a diagram illustrating operation timings of switches 248, 249, and 2414 in the signal transmission circuit illustrated in FIG. 24, and changes in an input voltage of a driven circuit 244.

26 is a diagram showing a waveform of an output voltage of the signal transmission circuit of the present invention shown in FIG. 24 and a waveform of an output voltage of the conventional signal transmission circuit shown in FIG. 27;

FIG. 27 is a diagram showing a configuration of a signal transmission circuit according to a conventional technique.

28 is a diagram illustrating a selection state of a selection switch of the conventional signal transmission circuit of FIG. 27 and an input voltage of a driven circuit 274. FIG.

FIG. 29 is a circuit diagram of a solid-state imaging device using a signal transmission circuit according to the present invention.

FIG. 30 is a timing chart showing a control procedure of the scanning circuit 299.

31 is a block diagram illustrating a configuration of a device to which the solid-state imaging device 2914 in FIG. 29 is applied.

[Explanation of symbols]

1, 2 constant voltage source 3 analog signal source 5 first amplifier circuit line 6a-6i first amplifier circuit 7 latch / intermediate holding circuit line 8a-8i latch circuit 9a-9i intermediate holding circuit 10 demultiplexer line 11a-11i demultiplexer 12 signal line array si1 to si4 signal line 14 second amplifier circuit array 15a to 15d second amplifier circuit 16 interpolation circuit 17A1 to 17A4, 17B1 to 17B3 third amplifier circuit 18a to 18g latch circuit 19 clock generation circuit 20 lower data processing circuit 21 arithmetic circuit 22 clock input terminal 23 output terminal

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Yoichi Okamoto 1006, Kazuma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-5-259917 (JP, A) JP-A-59- 172828 (JP, A) JP-A-56-104532 (JP, A) JP-A-58-34624 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1 / 00-1 / 88

Claims (15)

(57) [Claims] 1. A signal transmission circuit that receives an input signal, transmits a signal to a reception unit via a signal line, and outputs an output signal corresponding to the input signal. Capacitive means, a charge supply unit for providing a charge corresponding to the input signal to the first capacitive means, and a supply control means for controlling supply and stop of the charge from the charge supply unit, The receiving unit includes second capacitive means for receiving the electric charge from the first capacitive means, and a signal line for transmitting the electric charge accumulated in the first capacitive means to the second capacitive means. And a parasitic capacitance element on the signal line; and a transmission unit for controlling transmission and non-transmission of electric charge between the first capacitance unit and the signal line. A total capacitance value of the parasitic capacitive element is larger than a capacitance value of the first capacitive means; Charge supplying unit during non-transmission gives a charge to said first capacitive means, said supply control means during transmission the signal transmission circuit, characterized by stopping the supply of the charge. 2. The signal transmission circuit according to claim 1, further comprising a conversion unit that generates an output signal corresponding to the charge transferred to said second capacitive unit. 3. The first capacitive means has a first terminal and a second terminal, the second capacitive means has a first terminal and a second terminal, and the transmitting means has a first terminal and a second terminal. A switch for changing a connection state between the first terminal of the first capacitive unit and the first terminal of the second capacitive unit, wherein the second terminal of the first capacitive unit is connected to the second terminal of the second capacitive unit; The signal transmission circuit according to claim 1, wherein the signal transmission circuit is connected to a terminal. 4. The charge supply unit includes an amplifier, and the supply control unit includes a switch unit connected between an output terminal of the charge supply unit and the first capacitive unit.
3. The signal transmission circuit according to claim 1. 5. An amplifier for amplifying a signal at an input terminal and outputting the amplified signal to an output terminal, wherein the conversion means includes the second capacitive means; 3. The signal transmission circuit according to claim 2, further comprising capacitive means connected to the terminal. 6. The signal transmission circuit according to claim 2, wherein said conversion means has a variable capacitance. 7. An A / D converter for receiving an input voltage and outputting a digital signal corresponding to the input voltage, wherein the amplification means amplifies a voltage corresponding to a difference between the input voltage and a reference voltage; Holding capacitive means for holding a voltage output from the amplifying means, a signal line having a first terminal and a second terminal, a parasitic capacitive element on the signal line, the amplifying means and the holding capacitive means The first provided between
A transmitting means, a second transmitting means provided between the storage capacitive means and the first terminal of the signal line, and a charge connected to the second terminal of the signal line for transferring the stored charge of the storage capacitive means. Receiving capacitive means for receiving, in the first state, the first transmitting means is conductive, the second transmitting means is non-conductive, and in the second state, the first transmitting means The second transmission means is non-conductive, and the total capacitance value of the parasitic capacitive element and the receiving capacitive means is larger than the capacitance value of the holding capacitive means; An A / D converter characterized by reducing a constant. 8. A signal transmission method for receiving an input signal and outputting an output signal corresponding to the input signal, the method comprising: storing an electric charge corresponding to the input signal in a first capacitive means; Transferring the accumulated charge from the first capacitive means to the second capacitive means, wherein the accumulated charge is transferred from the first capacitive means to the second capacitive means through a signal transmission line. The total capacitance value of the parasitic capacitance element of the signal transmission line and the second capacitance means is larger than the capacitance value of the first capacitance means. A signal transmission method for controlling transmission and non-transmission of a signal between the capacitive means and the signal transmission line and stopping charge accumulation in the first capacitive means in the accumulation step. 9. The signal transmission method according to claim 8 , further comprising a conversion step of generating an output signal corresponding to the electric charge transferred to said second capacitive means. 10. The conversion step includes an amplifier that includes the second capacitive unit, amplifies a signal at an input terminal, and outputs the amplified signal to an output terminal. claim used and connected capacitive elements 9
2. The signal transmission method according to 1. 11. The signal transmission method according to claim 9 , wherein said converting step uses a variable capacitor. 12. A solid-state imaging device for receiving incident light and outputting an output signal corresponding to the incident light, comprising: a first capacitive means; and a charge corresponding to the incident light, the first capacitive means being provided to the first capacitive means. A charge supply unit, a second capacitive means, a first terminal connected to one terminal of the first capacitive means, a second terminal connected to the second capacitive means,
A signal line for transmitting the charge stored in the first capacitive means to the second capacitive means; a parasitic capacitive element on the signal line; and a predetermined terminal connected to the other terminal of the first capacitive means. And a transmission means connected between the electric potentials for controlling transmission and non-transmission of the electric charge accumulated in the first capacitive means, wherein a total capacitance of the parasitic capacitive element and the second capacitive means is provided. A solid-state imaging device, wherein a value is larger than a capacitance value of the first capacitive means. 13. The solid-state imaging device according to claim 12 , wherein said charge supply unit is a photodiode, and said first capacitive means is a parasitic capacitance of said photodiode. 14. The solid-state imaging device according to claim 12, further comprising a conversion unit that generates an output signal corresponding to the electric charge transferred to said second capacitive unit. 15. The conversion means includes the second capacitive means, an amplifier for amplifying a signal at an input terminal and outputting the amplified signal to an output terminal, and an amplifier connected to the input terminal and the output terminal. The solid-state imaging device according to claim 14 , comprising: a capacitive unit connected to the solid-state imaging device.