JPS636874A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS636874A
JPS636874A JP14942586A JP14942586A JPS636874A JP S636874 A JPS636874 A JP S636874A JP 14942586 A JP14942586 A JP 14942586A JP 14942586 A JP14942586 A JP 14942586A JP S636874 A JPS636874 A JP S636874A
Authority
JP
Japan
Prior art keywords
groove
film
polysilicon
substrate
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14942586A
Other languages
Japanese (ja)
Inventor
Fumitake Mieno
文健 三重野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14942586A priority Critical patent/JPS636874A/en
Publication of JPS636874A publication Critical patent/JPS636874A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To decrease transition regions, by performing a patterning process of a groove so that side walls of the groove in an oxidizing film extend to the same plane bearings as a substrate. CONSTITUTION:In a SiO2 film 14 formed on a (100) silicon substrate, a groove 23 is formed to expose the surface of the substrate by epitaxial growth. In this case, the plane bearing of the facet is made to be (10), and the groove 23 is formed in the direction vertical to the facet. Because the side walls 14a of the film 14 are of (100) bearings, singlecrystal silicon and polysilicon are made to grow respectively inside the groove 23 and on a silicon nitride film 21 by normal-pressure epitaxial growth using SiH4+H2. Therefore, generation of transition regions can be remarkably suppressed, together with miniaturization and high-speed performance in a bipolar transistor becoming available.

Description

【発明の詳細な説明】 〔概要〕 エピタキシャル・ポリシリコン同時成長において、成長
基板の面方位を規定することにより遷移領域を減少させ
る方法である。
DETAILED DESCRIPTION OF THE INVENTION [Summary] This is a method of reducing the transition region in epitaxial polysilicon simultaneous growth by defining the plane orientation of the growth substrate.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に関するもので、さらに
詳しく言えば、縦型のバイポーラトランジスタの製造に
際しエピタキシャル・ポリシリコンの同時成長において
遷移領域を減少させる方法に関するものである。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of reducing a transition region in simultaneous growth of epitaxial polysilicon during the manufacture of a vertical bipolar transistor.

〔従来の技術〕[Conventional technology]

従来のバイポーラトランジスタにおいては、エミ・ン夕
に対してベースが広すぎるために寄生容量が発生しトラ
ンジスタの動作速度を低下させる問題があり、その問題
を解決するためにエミッタとベースが第3図に示される
如く縦方向に配列された高速バイポーラトランジスタが
開発され、図中、11はシリコン基板、12はn+型埋
込層、13はn−エピタキシャル層、14は5i02膜
、15は単結晶シリコンのエピタキシャル層、16はポ
リシリコン膜、17はエミッタ、18は5iOz膜であ
る。 SiO2膜14に窓開けをなしてエピタキシャル
層13の表面を露出し、 5iHI+ )+2の反応ガ
スを用い常圧でエピタキシャル成長を行うと、エピタキ
シャル層13の上には単結晶シリコンが成長してエピタ
キシャル層15が作られ、他方5i02膜14の上には
ポリシリコン膜16が成長する(エピタキシャル・ポリ
シリコン同時成長)。この単結晶シリコン層15をベー
スとし、そこにn+型のエミッタ17を作ると、ベース
の広さは従来例のベースよりもかなり小になる利点があ
る。なお、ベース電極はp型にドープしたポリシリコン
月臭16によって引き出し、図において19はコレクタ
コンタクト層である。なお、B。
In conventional bipolar transistors, the base is too wide relative to the emitter and the base, which creates parasitic capacitance and reduces the operating speed of the transistor.To solve this problem, the emitter and base are A high-speed bipolar transistor arranged in the vertical direction was developed as shown in the figure. In the figure, 11 is a silicon substrate, 12 is an n+ type buried layer, 13 is an n- epitaxial layer, 14 is a 5i02 film, and 15 is a single crystal silicon. 16 is a polysilicon film, 17 is an emitter, and 18 is a 5iOz film. When a window is made in the SiO2 film 14 to expose the surface of the epitaxial layer 13 and epitaxial growth is performed at normal pressure using a reaction gas of 5iHI+)+2, single crystal silicon grows on the epitaxial layer 13, forming an epitaxial layer. On the other hand, a polysilicon film 16 is grown on the 5i02 film 14 (epitaxial polysilicon simultaneous growth). By using this single crystal silicon layer 15 as a base and forming an n+ type emitter 17 thereon, there is an advantage that the width of the base is considerably smaller than that of a conventional base. The base electrode is drawn out by a p-type doped polysilicon layer 16, and 19 in the figure is a collector contact layer. In addition, B.

E、Cはベース電極、エミ・ツタ電極、コレクタ電極で
ある。
E and C are a base electrode, an emitter/vine electrode, and a collector electrode.

ここで5i02膜14の上のポリシリコン成長について
本発明者が実験したところによると、第4図に示される
ようにSiO2膜上にはシリコンが付き難く、ポリシリ
コンは図に示すように不規則な凹凸をもって成長する。
According to the inventor's experiments regarding the growth of polysilicon on the 5i02 film 14, as shown in FIG. It grows with unevenness.

なお図において、20は(100)シリコン基板である
。しかし、5i02膜上に窒化シリコン膜(Si3N4
膜)21を成長すると、窒化シリコン膜上には第5図に
示す如くポリシリコンが付き易くなることが確かめられ
た。そこで、エピタキシャル・ポリシリコンの同時成長
においては、ポリシリコンを成長させるSiO2膜上に
窒化シリコン膜を前以って形成しておく。
In the figure, 20 is a (100) silicon substrate. However, the silicon nitride film (Si3N4
It was confirmed that when the film 21 was grown, polysilicon was easily deposited on the silicon nitride film as shown in FIG. Therefore, in simultaneous growth of epitaxial polysilicon, a silicon nitride film is formed in advance on the SiO2 film on which polysilicon is to be grown.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前記したエピタキシャル・ポリシリコン同時成長を第6
図を参照して説明すると、(100)シリコン基板20
上に作られるエピタキシャル層15とポリシリコン膜1
6との間に結晶欠陥のある部分すなわち遷移領域22が
作られることが確かめられた。
The above-mentioned epitaxial and polysilicon simultaneous growth was performed in the sixth step.
To explain with reference to the figure, (100) silicon substrate 20
Epitaxial layer 15 and polysilicon film 1 formed on top
It was confirmed that a portion with crystal defects, that is, a transition region 22, was formed between the two regions.

この部分は結晶欠陥があるために使うことができない部
分となり、それの幅だけエミッタ17が狭くなりデバイ
スの微細化の妨げとなる問題がある。
This portion cannot be used due to crystal defects, and the emitter 17 becomes narrower by the width thereof, which poses a problem of hindering miniaturization of the device.

本発明はこのような点に鑑みて創作されたもので、エピ
タキシャル・ポリシリコン同時成長において遷移領域を
減少させる方法を提供することを目的とする。
The present invention was created in view of these points, and it is an object of the present invention to provide a method for reducing the transition region in simultaneous epitaxial polysilicon growth.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明実施例断面図で、その(a)はエピタキ
シャル・ポリシリコン同時成長の中間過程を、その(b
)は同時成長終了後の構造を示す。
FIG. 1 is a cross-sectional view of an embodiment of the present invention, in which (a) shows an intermediate process of epitaxial and polysilicon simultaneous growth, and (b) shows an intermediate process of epitaxial polysilicon simultaneous growth.
) shows the structure after simultaneous growth.

本発明においては、(100)シリコン基板20に形成
された5i02膜に基板面を露出する溝23を形成する
ためのパターニングにおいて、その側壁14aの面方位
が基板の面方位と同じ<(100)になるように設定す
る。
In the present invention, in the patterning for forming the groove 23 that exposes the substrate surface in the 5i02 film formed on the (100) silicon substrate 20, the surface orientation of the side wall 14a is the same as the surface orientation of the substrate <(100). Set it so that

〔作用〕[Effect]

本発明者は実験によって前記した遷移領域の発生はエピ
タキシャル層のファセットにゝも原因があり、エピタキ
シャル成長の途中の状態を示す第7図の従来例断面図を
参照すると、(100)基板を用いたとき5iOz膜1
4の側壁14aが(110)に平行であるとき、(11
1)面または(221)面のファセットが出ることをつ
きとめた。
The present inventor has experimentally found that the occurrence of the transition region described above is also caused by the facets of the epitaxial layer. Referring to the cross-sectional view of a conventional example shown in FIG. Time 5iOz film 1
When the side wall 14a of 4 is parallel to (110), (11
1) It was found that facets of planes or (221) planes appeared.

上記した本発明の方法によると、(100)基板に対し
て5i02DAO側914aが(100)方向にあるよ
うパターニングしであるので、遷移領域が著しく減少す
るのである。
According to the method of the present invention described above, since patterning is performed so that the 5i02DAO side 914a is in the (100) direction with respect to the (100) substrate, the transition region is significantly reduced.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を詳細に説明すイ
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

本発明の方法によると、(100)シリコン基板上に形
成されたSiO+膜14にエピタキシャル成長のための
基板表面を露出する溝23を形成するにおいて、第2図
(alに示される如くファセットの面方位を(100)
にとり、ファセットに垂直方向に溝23を形成する。
According to the method of the present invention, in forming the grooves 23 that expose the substrate surface for epitaxial growth in the SiO+ film 14 formed on the (100) silicon substrate, the surface orientation of the facets as shown in FIG. (100)
Then, grooves 23 are formed in the facets in the vertical direction.

または、第2図(blに示されるように、−般のウェハ
がそうであるように(100)のシリコン基板20のフ
ァセットが(110)方位にあるときは、ファセットに
対して45°伸けて溝23を形成する。そのためには、
溝23を作るためのマスクを第2図fatの場合に相対
的に45°傾けるとよい。
Or, as shown in FIG. 2 (bl), when the facets of the (100) silicon substrate 20 are in the (110) direction, as is the case with general wafers, the angle is extended by 45 degrees with respect to the facets. to form the groove 23. To do so,
It is preferable to tilt the mask for forming the groove 23 by 45 degrees relative to the case of fat in FIG.

このようにして溝23を形成すると、第1図(alに示
される5i02股14の側壁14aは(100)方位に
あるから、そこに示されるように5iHq 十fi2を
用いる常圧エピタキシャル成長で溝23内には単結晶シ
リコンが成長し、窒化シリコン膜上にはポリシリコンが
成長する。第1図fatはエビタキシャル成長途中の状
態を示すもので、同成長が終了しエピタキシャル層が5
000人の厚さに形成されたとき第1図fblに示され
る構造が得られ、遷移領域はほとんど認められなかった
。なお第り図(ト))においては、ポリシリコン膜16
の表面を酸化して5i021i18が形成された状態が
示される。ポリシリコン膜16はベース電極引出し部と
するのでp型にドープする。このようにエピタキシャル
・ポリシリコンの同時成長をなした後に第3図に示され
るバイポーラトランジスタを形成する。
When the groove 23 is formed in this way, the side wall 14a of the 5i02 crotch 14 shown in FIG. Single-crystal silicon grows on the silicon nitride film, and polysilicon grows on the silicon nitride film. Figure 1 fat shows the state in the middle of epitaxial growth, and when the growth is completed and the epitaxial layer is 5.
When formed to a thickness of 1,000 mm, the structure shown in FIG. 1 fbl was obtained, with almost no transition region observed. Note that in FIG.
The state in which 5i021i18 is formed by oxidizing the surface of is shown. Since the polysilicon film 16 is used as a base electrode extension part, it is doped to be p-type. After simultaneous growth of epitaxial polysilicon in this manner, the bipolar transistor shown in FIG. 3 is formed.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように本発明によれぼ、エピタキシャル
・ポリシリコン同時成長において、従来問題となった遷
移領域の発生が著しく抑えられ、バイポーラトランジス
タの微細化と高速化に有効である。
As described above, the present invention significantly suppresses the generation of transition regions, which has been a problem in the past, in simultaneous epitaxial polysilicon growth, and is effective in miniaturizing and increasing the speed of bipolar transistors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(alと(b)は本発明実施例断面図、第2図(
alと山)は本発明実施例平面図、第3図は高速バイポ
ーラトランジスタの断面図、第4図は従来例の問題点を
示す断面図、第5図は従来例の改良例の断面図、 第6図は従来例断面図、 第7図は従来例断面図である。 第1図ないし第7図において、 11はシリコン基板、 12は埋込層、 13はエピタキシャル層、 14は 5i02膜、 15はエピタキシャル層、 16はポリシリコン膜、 17はエミッタ、 18は SiO2膜、 19はコレクタコンタクト層、 20は(100)シリコン基板、 21は窒化シリコン侯、 23は溝である。 ν                   !(Y’)
          − ヘー 島土バイ符うトランジスタ涌゛命国 第 3 ミ」 狭象例の藺局主を左、すの 第4図 イえ天側の改良利耕[有]口 1」−一1ヒう列#riシロ] 36図 凌豪例虹i圀 第7図
Figures 1 (al and b) are sectional views of embodiments of the present invention, Figure 2 (
3 is a cross-sectional view of a high-speed bipolar transistor, FIG. 4 is a cross-sectional view showing problems in the conventional example, and FIG. 5 is a cross-sectional view of an improved example of the conventional example. FIG. 6 is a sectional view of a conventional example, and FIG. 7 is a sectional view of a conventional example. 1 to 7, 11 is a silicon substrate, 12 is a buried layer, 13 is an epitaxial layer, 14 is a 5i02 film, 15 is an epitaxial layer, 16 is a polysilicon film, 17 is an emitter, 18 is a SiO2 film, 19 is a collector contact layer, 20 is a (100) silicon substrate, 21 is a silicon nitride layer, and 23 is a groove. ν! (Y')
- Transistors appear on the island of Hei, the land of life, number 3. The narrow example of the land is on the left, and Figure 4 is the improvement of the heaven side. Column #ri Shiro] Figure 36 Ling Hao Example Rainbow i Country Figure 7

Claims (1)

【特許請求の範囲】[Claims] 半導体基板(20)上に形成された酸化膜(14)に基
板表面を露出する溝(23)をパターニングし、溝内に
はエピタキシャル成長を、酸化膜(14)上にはポリシ
リコンを同時に成長する方法において、酸化膜(14)
の溝に面する側壁(14a)が基板と同じ面方位に延び
る如く溝(23)をパターニングすることを特徴とする
半導体装置の製造方法。
Patterning a groove (23) exposing the substrate surface in an oxide film (14) formed on a semiconductor substrate (20), growing epitaxially in the groove and simultaneously growing polysilicon on the oxide film (14). In the method, an oxide film (14)
A method of manufacturing a semiconductor device, comprising patterning a groove (23) so that a side wall (14a) facing the groove extends in the same plane direction as a substrate.
JP14942586A 1986-06-27 1986-06-27 Manufacture of semiconductor device Pending JPS636874A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14942586A JPS636874A (en) 1986-06-27 1986-06-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14942586A JPS636874A (en) 1986-06-27 1986-06-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS636874A true JPS636874A (en) 1988-01-12

Family

ID=15474825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14942586A Pending JPS636874A (en) 1986-06-27 1986-06-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS636874A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01272460A (en) * 1988-04-26 1989-10-31 Nippon Joho Kagaku Kk Method and apparatus for generating character
JPH02250189A (en) * 1989-03-24 1990-10-05 Nippon Joho Kagaku Kk Method and device for generating character
JPH02250089A (en) * 1989-03-24 1990-10-05 Nippon Joho Kagaku Kk Method for removing quantization error in character generation with outline font by element
US5257344A (en) * 1991-05-08 1993-10-26 Brother Kogyo Kabushiki Kaisha Character outline processor using relatively small memory storing coordinate data groups for different outlines of same character, and common attribute flag data
JPH08147484A (en) * 1994-11-21 1996-06-07 Nippon Joho Kagaku Kk Character generating method
WO2000017423A2 (en) * 1998-09-21 2000-03-30 IHP GMBH Innovations for High Performance Microelectronics Institut für innovative Mikroelektronik Method for producing an amorphous or polycrystalline layer on an insulating region

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01272460A (en) * 1988-04-26 1989-10-31 Nippon Joho Kagaku Kk Method and apparatus for generating character
JPH0552793B2 (en) * 1988-04-26 1993-08-06 Nippon Joho Kagaku Kk
JPH02250189A (en) * 1989-03-24 1990-10-05 Nippon Joho Kagaku Kk Method and device for generating character
JPH02250089A (en) * 1989-03-24 1990-10-05 Nippon Joho Kagaku Kk Method for removing quantization error in character generation with outline font by element
US5257344A (en) * 1991-05-08 1993-10-26 Brother Kogyo Kabushiki Kaisha Character outline processor using relatively small memory storing coordinate data groups for different outlines of same character, and common attribute flag data
JPH08147484A (en) * 1994-11-21 1996-06-07 Nippon Joho Kagaku Kk Character generating method
WO2000017423A2 (en) * 1998-09-21 2000-03-30 IHP GMBH Innovations for High Performance Microelectronics Institut für innovative Mikroelektronik Method for producing an amorphous or polycrystalline layer on an insulating region
WO2000017423A3 (en) * 1998-09-21 2000-06-22 Inst Halbleiterphysik Gmbh Method for producing an amorphous or polycrystalline layer on an insulating region

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