JPS6368193U - - Google Patents
Info
- Publication number
- JPS6368193U JPS6368193U JP16325586U JP16325586U JPS6368193U JP S6368193 U JPS6368193 U JP S6368193U JP 16325586 U JP16325586 U JP 16325586U JP 16325586 U JP16325586 U JP 16325586U JP S6368193 U JPS6368193 U JP S6368193U
- Authority
- JP
- Japan
- Prior art keywords
- timing
- level data
- output
- channel
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Description
図面はこの考案の一実施例を示すもので、第１
図は回路構成を示すブロツク図、第２図は各クロ
ツクの動作タイミングを示すタイミングチヤート
、第３図は信号処理部内での処理内容を示すフロ
ーチヤート、第４図はマイクロコンピユータでの
処理内容を示すフローチヤートである。
１０……信号処理部、１１……Ｓ／Ｐ変換回路
、１２……タイミング信号発生回路、１３……ラ
ツチ回路（Ｌ）、１４……比較回路、１５……ラ
ツチ回路（Ｒ）、１９……出力ポート、２０……
マイクロコンピユータ、２１……表示駆動回路、
２２……レベル表示部。
The drawing shows one embodiment of this invention.
Figure 2 is a block diagram showing the circuit configuration, Figure 2 is a timing chart showing the operation timing of each clock, Figure 3 is a flowchart showing the processing contents in the signal processing section, and Figure 4 shows the processing contents in the microcomputer. This is a flowchart. 10... Signal processing section, 11... S/P conversion circuit, 12... Timing signal generation circuit, 13... Latch circuit (L), 14... Comparison circuit, 15... Latch circuit (R), 19... ...Output port, 20...
Microcomputer, 21...display drive circuit,
22...Level display section.
Claims (1)
ベルデータを各チヤンネル毎に出力するレベルデ
ータ出力手段と、 上記複数のチヤンネルに対応する時分割タイミ
ング信号を発生するタイミング発生手段と、 このタイミング発生手段のタイミング信号に従
い、上記レベルデータ出力手段から出力されるチ
ヤンネル毎のレベルデータの一定時間内のピーク
データをラツチするラツチ手段と、 このラツチ回路が一定時間毎に出力するチヤン
ネル毎のピークデータを上記タイミング発生手段
のタイミング信号に従つて時分割的に出力する出
力ポートと、 この出力ポートの出力するピークデータに従つ
て各チヤンネル毎のレベルデータの表示制御を行
なう表示制御手段と を具備したことを特徴とするレベル表示装置。[Claims for Utility Model Registration] Level data output means for outputting digitally recorded audio level data of multiple channels for each channel; and timing generation means for generating time-sharing timing signals corresponding to the plurality of channels. , a latch means for latching the peak data within a certain period of time of the level data for each channel output from the level data output means according to the timing signal of the timing generating means; an output port that outputs the peak data of the above in a time-divisional manner according to the timing signal of the timing generating means; and a display control means that controls the display of the level data for each channel according to the peak data output from the output port. A level display device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16325586U JPS6368193U (en) | 1986-10-24 | 1986-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16325586U JPS6368193U (en) | 1986-10-24 | 1986-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6368193U true JPS6368193U (en) | 1988-05-09 |
Family
ID=31091284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16325586U Pending JPS6368193U (en) | 1986-10-24 | 1986-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6368193U (en) |
-
1986
- 1986-10-24 JP JP16325586U patent/JPS6368193U/ja active Pending
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