JPS636804B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counting device used in a measuring device and the like, and for example, to a device that counts the number of pulses of a pulse signal in combination with an encoder device used for length measurement and angle measurement.

In recent years, as encoders used for length measurement and angle measurement, there are, for example, photoelectric type encoders. A photoelectric linear encoder or a rotary encoder is generally provided with a main scale that is attached to a moving body or a rotating body and moves together with the main scale, and an index scale that is arranged to face the main scale. A light source and a photoelectric converter are provided to sandwich the index scale. Each scale is provided with a so-called lattice pattern in which light transmitting parts and light blocking parts are different from each other. Therefore, length measurement,
Or, when the object to be measured moves or rotates and the light shielding parts of the main scale grating and the index scale grating overlap, the light from the light source passes through each scale and reaches the photoelectric converter at the same time. .

At this time, the photoelectric signal is at its maximum. Furthermore, when the light shielding part and the transmitting part of the main scale and index scale overlap, almost no light from the light source reaches the photoelectric converter, so the photoelectric signal becomes minimum. As described above, the photoelectric signal becomes a pulsed signal. Generally, the lattice pattern of each scale is provided at a constant pitch, so by counting the number of pulses of this photoelectric signal, the amount of movement or rotation can be determined. A counting device can be obtained by shaping the photoelectric signal outputted in this way into a pulse, that is, a digital signal, counting the number of pulses of this signal using a suitable digital counter, and displaying the result, for example.

However, in recent years, the values measured by length or angle with such encoders are not only displayed as they are, but also perform predetermined calculations based on the measured values and display the results. Various functions such as determining whether a predetermined measurement value has been reached have become required. For this reason, encoders have come to be used in combination with appropriate arithmetic and processing devices.

This arithmetic processing device is often a digital electronic computer, that is, a computer, but with measuring instruments such as encoders, both arithmetic and processing are limited to specific tasks, so there is a need for computation power and processing capacity. A paramicrocomputer is used. By the way, there are various types of microcomputers, but at least they have a program that describes a certain calculation or processing method, data required in advance for the calculation or processing, or data that can be obtained by calculation or processing according to the program. It shall have means for storing the data etc.

Therefore, an encoder that measures length and angle using a microcomputer will be briefly described. Generally, calculations are performed by a microcomputer,
The processing is performed in units of a predetermined number of bits, for example 4 bits, 8 bits, etc. In other words, it is parallel data. However, as mentioned above, the signal from the encoder is just a pulse signal, that is, serial data. Therefore, up-down counters have traditionally been used to convert pulse signals from encoders into signals that can be directly handled by microcomputers. In the encoder,
A signal for determining the direction of movement or rotation is separately output. Therefore, by this discrimination signal,
The number of pulses of the encoder pulse signal is counted by switching the up-down counter to an up-counter or a down-counter. The microcomputer is adapted to read the count data of this up-down counter from the input port. However, as mentioned above, on the microcomputer side, in addition to reading count data, interrupt processing is used to perform calculations or processing operations according to a predetermined program. Generally, when an interrupt request occurs in a microcomputer, the calculation or processing program that was being executed is temporarily stopped, and other work (another program) is executed. When the interrupt processing is finished, the original program is resumed. Therefore, in a conventional counting device using a microcomputer and an up-down counter, the counting data of the up-down counter is directly read until the up-down counter overflows or underflows, and when a carry or borrow signal is output, the micro The computer was interrupted and was calculating the upper digits of the count data.

For example, if the up-down counter is of a 4-bit binary output format, the up-down counter counts the number of pulses of the pulse signal from the encoder and outputs a carry or borrow signal every 16 pulses. At the same time, the up-down counter continues counting pulse signals. When the microcomputer is interrupted by a carry or borrow signal of the up-down counter, it adds 1 to the previous high-order count data if it is a carry signal, and adds 1 to the previous high-order count data if it is a borrow signal. Subtract 1 from the data,
Data was obtained by overlapping the count data of the up-down counter with the count data up to that point.

However, as the number of pulses per unit time of the encoder pulse signal increases, the interrupt processing time of the microcomputer becomes a problem. In other words, the interrupt processing time largely depends on the program, but for example, if the encoder scale vibrates at a position where a carry signal is output and the carry and borrow signals are repeatedly output in a short period of time, the interrupt processing may take longer. This results in a drawback that the tracking becomes impossible and, as a result, a counting error occurs.

On the other hand, if an up-down counter with sufficient counting capacity is used, it is expensive.

SUMMARY OF THE INVENTION An object of the present invention is to solve these drawbacks and provide a counting device that does not increase the capacity of counting means such as an up-down counter and does not cause counting errors.

In order to achieve the object, the counting device of the present invention includes a measuring means that outputs a number of pulses corresponding to a measured quantity, a maximum count value that is smaller than the number of pulses corresponding to the maximum measured quantity, and a measuring means that outputs a number of pulses corresponding to a measured quantity, a counting means for counting the number of pulses from the counting means, a holding means capable of holding a count output signal of the counting means, outputting a start signal before the count value by the counting means exceeds a maximum count value, and after outputting the start signal. digital calculation means for accumulating the count output signals held by the holding means; and digital calculation means for causing the holding means to hold the count output signals of the counting means based on the start signal; and control means for resetting the counting means to initialize the counting output signal before the pulse signal is output.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. A linear encoder is constituted by a scale section 1 which is provided with a main scale and moves together with the moving object, and a detection section 2 which is provided with an index scale. When the scale section moves, the detection section 2 outputs a detection signal as shown in FIG. 1a. The detection signals are two sinusoidal signals with a phase difference of approximately 90°. This allows the direction of movement of the scale section 1 to be detected, and as described above, two sets of main scale lattice patterns are provided, and their pitches are shifted from each other by an amount corresponding to a phase difference of 90 degrees. For example, as shown in Figure 1a, when the phase of the detection signal _S1 lags the phase of the detection signal S2, the scale _{section 1} moves in one direction, and when the phase relationship is reversed, the scale section 1 moves in the other direction. It turns out. The detection signals S ₁ and S ₂ are converted by the amplification and waveform shaping circuit 3 into square wave signals S ₁ ' and S ₂ ' that can be digitally processed, as shown in FIG. 1b. signal
The number of pulses S ₁ ′ and S ₂ ′ is proportional to the moving distance of the scale section 1. Furthermore, the frequencies of the signals S ₁ ' and S ₂ ' are proportional to the moving speed of the scale section 1. This signal S ₁ ′,
S ₂ ' is converted by the direction discrimination pulsing circuit 4 into two series of pulse signals, an up count pulse and a down count pulse, necessary for the up down counter 5 at the next stage. That is, by determining the direction, for example, when moving in one direction, only an up count pulse is output, and when moving in the other direction, only a down count pulse is output. Furthermore, these count pulses are output in synchronization with the first clock signal φ1 output from the two-phase clock oscillator 10. Although the details will be described later, the frequency of the two-phase clock signal is based on the reference clock of the microcomputer 7, and generally the frequency of the two-phase clock signal is based on the reference clock of the microcomputer 7.
The frequency is set sufficiently higher than the frequencies of S ₁ ′ and S ₂ ′. The up-down counter 5 operates to increase the count value by the above-mentioned up count pulse and to decrease the count value by the down count pulse.

Incidentally, the up-down counter 5 can be reset by a reset signal. The count data of the up-down counter 5 is input to the latch circuit 6 at the next stage. The latch circuit 6 holds input data in response to a latch signal. This state is called a latched state. Further, when the latch signal is not input, the count data of the up-down counter 5 appears as is at the output of the latch circuit 6. Note that this state is referred to as an active state. The microcomputer 7 receives the output data of the latch circuit 6 from the input port section. The count data read by the microcomputer 7 is subjected to predetermined calculations and processing, and the results are displayed on the display section 8. While the microcomputer 7 is performing work such as calculations and processing, more precisely, the microcomputer 7 starts from the time when the microcomputer 7 reads the count data of the latch circuit 6 via the input port section. The signal is output to the synchronization circuit 9. The synchronization circuit 9 synchronizes the second clock signal φ2 output from the two-phase clock oscillator 10 with the start signal.
It outputs the reset signal and latch signal as described above.

As described above, the microcomputer 7 operates according to a program that outputs a start signal immediately before reading the count data of the input port section. The details will be described later.

FIG. 2 is a circuit diagram specifically showing the main parts in the block diagram of FIG. 1. The operation of this circuit,
The operation and operation will be explained based on the time chart shown in FIG. The direction determination pulse generation circuit 4 receives pulse signals as shown in FIG. 16 from terminals 11 and 12.
This pulse signal corresponds to signals A and B in FIG. In addition, in FIG. 3, at time T, scale section 1
Assume that the moving direction of is reversed. Therefore, the phase relationship between signals A and B also becomes reversed from time T. A D flip-flop (hereinafter referred to as D-) inputs signals A and B.
FF) 13 and D-FF 14 input the first clock signal φ1 of the two-phase clock oscillator 10 from CK, convert the signals A and B into signals synchronized with the rise of the clock signal φ1, and output the signals. The converted and output signals become signals C and D in FIG. 3. Furthermore, D-FF15 and D-FF16 input signals C and D, respectively, and latch the states of signals C and D at the rising edge of clock signal φ1. Therefore,
As shown in FIG. 3, the output signal E of the D-FF 15 and the output signal F of the D-FF 16 are delayed by one clock of the clock signal φ1 with respect to the signals C and D, respectively. In other words, it constitutes a synchronous delay circuit using D-FF.

The output signals of each D-FF are NOT17, 18,
Pulsed by AND19-26 and OR27, 28, according to the moving direction of the scale section 1,
Two series of signals are outputted by OR27 and 28. These two series of signals are shown as signals G and H in FIG. The signals G and H are hereinafter referred to as count pulses G and H. Count pulses G and H are synchronized with clock signal φ1 when the states of input signals A and B change, and the signals are output for a length of one clock period. Here, when the count pulse G is output, it is assumed that the scale section 1 moves in the positive direction, and when the count pulse H is output, it is assumed that the scale section 1 moves in the negative direction.

These count pulses G and H are counted by an up-down counter 5. The input UC of the up-down counter 5 is an up-count input, and the input DC is a down-count input. Therefore, when the count pulse G is output, the up-down counter 5 performs an up-count operation and outputs the outputs _Q1 to _Q4 in binary format or BCD format.
Outputs count data obtained by adding the number of pulses of count pulse G. Note that output Q ₁ is LSB, output Q ₄ is
MSB. Furthermore, when the count pulse H is input to the input DC, the up-down counter 5 performs a down-count operation and outputs count data obtained by subtracting the number of pulses of the count pulse H to the outputs _Q1 to _Q4 . The up-down counter 5 clears the count data of the outputs _Q1 to _Q4 by setting the input CL to "H" level.

The count data of the up-down counter 5 is input to inputs D ₁ to _{D 4} of the latch circuit 6. The latch circuit 6 is in a latch state when the input CK is at "H" level. Therefore, when the input CK is at the "L" level, the count data of the inputs _D1 to _D4 appear as they are on the outputs _Q1 to _Q4 . When the input CK reaches the "H" level, the count data at that time is held and output to the outputs _Q1 to _Q4 .

On the other hand, the microcomputer 7 inputs the outputs Q ₁ to _{Q 4} of the latch circuit 6 to input port sections PD ₁ to _{PD 4} . Generally, the input/output ports (I/O ports) of a microcomputer are controlled by a program. Therefore, even if input data is simply added to the port section, the microcomputer will not read that data internally. Therefore, the microcomputer 7 operates according to a program that reads input data from the ports PD ₁ to _{PD 4} as appropriate. At the same time, microcomputer 7
outputs a signal representing the start of input from the port units PD ₁ to _{PD 4} to the port PC. The signal representing this start is designated as signal PC. As mentioned above, the signal PC includes the signal J for clearing the up-down counter 5 and the signal I for latching the latch circuit 6.
is input to the synchronization circuit 9 which outputs. This synchronization circuit 9 determines the timing of outputting the signal J and the signal I.
Count pulses G, H and second clock signal φ
It works to synchronize with 2. In addition, the clock signal φ
2 has a phase difference of about 180° from the clock signal φ1, as shown in FIG.

This synchronous circuit 9 includes a NAND 31 in negative logic notation,
32, R-S flip-flop (hereinafter referred to as R-S flip-flop)
SFF. ), a one-shot multivibrator 30, etc.

The NAND 33 receives the clock signal φ2, the output signal K of the NOR 34 which performs a NOR operation on the count pulses G and H, and the signal PC. The output signal K of NOR34 and the output signal L of NAND33 are shown in Fig. 3.
The signals will look like K and L. The signal PC becomes the reset input of R-SFF, and the signal L becomes the set input. Therefore, the output signal I of R-SFF is the signal PC
When is at the "L" level, it is at the "L" level regardless of the state of the output signal L of the NAND 33.
After the signal PC goes to the "H" level, the signal I goes to the "H" level from the time when the state of the signal L changes for the first time, and the latch circuit 6 performs a latching operation.
The one-shot multivibrator 30 outputs a signal J that is at the "H" level for a certain period of time t after the rise of the signal I, and the up-down counter 5 is cleared by the "H" level of the signal J. The time t is
As shown in signal J in FIG.
It is set to be shorter than half of one clock period of 2. This is because, as mentioned earlier, the phase difference between the clock signals φ1 and φ2 is about 180°.
In other words, the scale section 1 moves at high speed, and the state changes of the signals A and B are almost equal to the 2nd half of the clock signal φ1.
When occurring every clock period, the count pulse G,
H is a pulse signal with a duty ratio of approximately 50%. Therefore, the timing at which signal J is output is
Since it is synchronized with the rising edge of clock signal φ2,
If the time t of the "H" level of the signal J is longer than half the clock cycle, the input of the count pulse G or H will conflict with the time for clearing the up-down counter 5 by the signal J, and as a result, the counting will be delayed. I end up making a mistake. Therefore, in the example,
Time t is set to be shorter than half the clock period.

As mentioned above, signal I is a latch signal and signal J is a clear signal, but in FIG.
The output timings of the two signals match, and the latch operation and clear operation appear to be in conflict, but
Since the signal J is obtained via the one-shot multivibrator 30, there is actually a slight time delay, and the up-down counter 5 is cleared immediately after the latch circuit 6 starts latching.

In this way, the microcomputer 7 receives the signal from the PC.
When outputted, the count data is held in the latch circuit 6. Then, this held data is read and accumulated with the data counted up to that point.
However, during this time, the up-down counter 5 is cleared once and is performing a counting operation.
Therefore, as soon as the output of the signal PC ends, the latch circuit 6 also becomes active, and the output of the signal PC becomes active.
The number of pulses counted during the period when was output is
It is output to the outputs Q ₁ to _{Q 4} of the latch circuit 6.

As described above, the start of reading by the microcomputer 7 is forcibly timed between the pulses of the count pulses, and at the same time the up-down counter is cleared once, so the count pulses are counted reliably. It turns out.

FIG. 4 is a flowchart of the simplest program for operating the microcomputer 7 in this embodiment as described above. As mentioned above, the microcomputer has an accumulator, and normal operations are performed by this accumulator.

In Figure 4, this accumulator (hereinafter referred to as a register) is designated as Reg, and the port section for inputting count data is designated as Reg.
The port unit that outputs PD and start signal PC is expressed as PC. This flowchart will be explained below based on the timing chart of FIG. When starting this program, it is necessary to reset the register Reg of the microcomputer. Although it is reset to 0 here, it may be reset to a specific value. This reset step
After step 40 is completed, step 41 for initial clearing of the up-down counter 5 is performed, but as mentioned earlier, the clearing operation is performed by the output of the signal PC.
Set the port PC to “H” level once, then “L”
You can set it to the level. Measurement using the encoder is now possible. After that, it is assumed that signals A and B as shown in the timing chart of FIG. 3 are outputted from the encoder. As mentioned above, the encoder is
It moves in the positive direction and outputs a count pulse G. The up-down counter 5 counts the count pulses G as 1, 2, 3, etc. in FIG.
However, it is assumed that the microcomputer 7 outputs the reading start signal PC during the first pulse of the count pulse G (step 42 in FIG. 4). Then, after waiting for the end of the first pulse, the latch circuit 6 operates as described above, and the binary or BCD format output corresponding to the count data 1 is held at the output of the latch circuit 6. At the same time, the up-down counter 5 is cleared to 0 by the signal J. Then, in step 43 in Figure 4, the port
Count data 1 applied to PD and latched;
Since the contents of the register Reg up to that point are added and the result is stored in the register Reg, the contents of the register Reg become 1 at this point. During execution of this calculation, the up-down counter 5 starts counting from the next pulse. That is, the second and third pulses of the count pulse G are counted, and the output is 2. However, at time T in FIG. 3, the direction of movement of the encoder changes. Since the count pulse H is output after time T, the up-down counter 5 performs a subtraction operation starting from the fourth pulse.
Therefore, when the fourth pulse is input, the output of the up-down counter 5 becomes 1. step 43
When the calculation is completed and the signal PC goes to "L" level in step 44, the latch circuit 6 becomes active, and the up-down counter 5 at that time
output, that is, 1. Then step
At step 45, an operation is performed to display the contents of the register Reg, that is, the distance corresponding to 1. Step 45 is started, and while step 42 is executed again, the up-down counter 5 counts the count pulses H. When the fourth pulse is input, the output of the up-down counter 5 is 1, and when the fifth pulse is input, the output becomes 0. Furthermore, upon input of the sixth pulse, the up-down counter 5 underflows and outputs 15 (that is, all 4 bits are "H"). These 15 are
It means -1 expressed in two's complement. Therefore, the third
Although not shown in the figure, when step 42 is executed again after the sixth pulse is input, the latch circuit 6 similarly holds this value 15 and registers it.
The contents of Reg are the counting data up to that point, here 1
Then, add this 15 and get 0 (there will be an overflow since it is 4 bits). That is, at this point (when the sixth pulse is input), the moving distance of the encoder is measured to be zero.

As described above, measurement is performed by executing the program as shown in the flowchart shown in FIG. 4, but the execution time from step 42 to step 45 is faster than the predetermined moving speed of the encoder. It is defined as follows. That is, when reading starts in step 42, the up-down counter 5 is cleared and starts counting again from 0, but by the time the next reading starts, the up-down counter 15 has counted from 0 more than once. Naturally, this will lead to counting errors. Therefore, in this case, the up-down counter 5 and the latch circuit 6 shown in the embodiment may have 4 bits or more, for example, 8 bits. The microcomputer 7 should either be able to handle 8 bits directly, or if it is 4 bits, the upper and lower 4 bits of the 8 bit latch circuit should be read separately and converted into 8 bit equivalent data using a program. What you need to do is to do something like Further, although the two-phase clock signal in this embodiment is generated by the oscillator 10, it goes without saying that it can also be used as a reference clock signal for a microcomputer. However, a phase difference between the clock signals φ1 and φ2 is always required. Furthermore, although a microcomputer is used for measurement in this embodiment, if the measurement data is simply to be displayed, an accumulator equivalent to a register,
It is also possible to provide a circuit for outputting a reading start signal PC, so that the signal PC is generated every fixed number of pulses of the clock signal φ1 or φ2, and the counted data is read into the accumulator.

Note that the program flowchart shown in Figure 4 is a simple one to explain the basic operation, and in reality, the maximum counting speed (encoder movement speed) as described above Other tasks (calculations, processing) can be performed depending on the situation.

As described above, according to the counting device according to the present invention, counting means such as an up-down counter and holding means such as a latch circuit are combined without using interrupt processing, and the counting data up to that point of the counting means is stored in the holding means. At the same time, the counting means is reset and immediately counts the next pulse. Therefore, pulse signals from measuring means such as encoders are reliably counted, and since the counting means continues counting even while the digital calculating means is performing accumulation, the measured quantity is not reversed. It has the advantage of being able to count at high speed. Therefore, by applying the present invention to a non-contact type photoelectric encoder in particular, its high-speed movement characteristics can be fully utilized.

Furthermore, when a microcomputer is used as the digital calculation means, the microcomputer does not use interrupt processing to read count data, so it has the advantage that interrupt processing can be used for other purposes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 1a is a diagram showing the output signal of the detection section 2 in FIG. 1 in principle, and FIG. 1b is a diagram showing the output signal of the detection section 2 in FIG. FIG. 3 is a diagram showing a signal obtained by waveform shaping an output signal. 2 is a circuit connection diagram of the main blocks in the block diagram shown in FIG. 1, and FIG. 3 is a timing chart showing signals of various parts in the circuit of FIG. 2. FIG. 4 is a flow chart for operating the microcomputer used in the example. [Explanation of symbols of main parts] Measurement means...1,
2, 3, Counting means...5, Holding means...6, Digital calculation means...7, Control means...9.

Claims (1)

[Scope of Claims] 1. A measuring means that outputs a number of pulses corresponding to a measured quantity, and a number smaller than the number of pulses corresponding to the maximum measured quantity as a maximum count value, and counting the number of pulses from the measuring means. a counting means capable of holding a count output signal of the counting means; a holding means capable of holding a count output signal of the counting means; outputting a start signal before a count value by the counting means exceeds a maximum count value; digital calculation means for accumulating the count output signal of the counting means; and based on the start signal, the holding means is made to hold the count output signal of the counting means, and after the holding, the pulse signal is also output. and control means for resetting the counting means so as to initialize the counting output signal beforehand. 2. The control means controls the first
an oscillation circuit that outputs a clock signal and a second clock signal; 2. The apparatus according to claim 1, further comprising a synchronization circuit for outputting a holding signal for activating the holding means and a reset signal for resetting the counting means. 3. The measuring means includes a photoelectric linear encoder or a rotary encoder, and the encoder outputs two detection signals having a predetermined phase difference and consisting of a number of pulses corresponding to the amount of movement or rotation. The device according to claim 2, characterized in that: 4. The measuring means generates a signal as the pulse signal that is proportional to the number of pulses of the detection signal and synchronized with the second clock signal, and determines the moving direction of the encoder from the phase difference between the two detection signals. , or a direction determining pulse circuit that determines the rotational direction and, according to the determination, selectively distributes and outputs the pulse signal into two series. Device. 5. The counting means is an up-down counter that increases the counting output signal by one series of pulse signals among the pulse signals and decreases the counting output signal by the pulse signal of the other series of the pulse signals. 5. The device according to claim 4, characterized in that: 6. The digital calculation means includes a port unit that inputs the count output signal of the up-down counter held in the holding unit, an arithmetic unit that includes an accumulator that accumulates digital data of the input port unit, and the start The device according to claim 5, characterized in that it is a microcomputer that includes an output port unit that outputs a signal, and that can control the operations of the port unit, arithmetic unit, and output port unit by a program. .