JPS5729911A - Counting device - Google Patents
Counting deviceInfo
- Publication number
- JPS5729911A JPS5729911A JP10369380A JP10369380A JPS5729911A JP S5729911 A JPS5729911 A JP S5729911A JP 10369380 A JP10369380 A JP 10369380A JP 10369380 A JP10369380 A JP 10369380A JP S5729911 A JPS5729911 A JP S5729911A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- inputted
- counter
- latched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/22—Analogue/digital converters pattern-reading type
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
Abstract
PURPOSE:To execute counting exactly and at a high speed without using an interruption processing, by constituting device so that a count data of an up-down counter is latched by a latching circuit, and also the counter is cleared and the next input pulse is counted. CONSTITUTION:A signal from a linear encoder consisting of a scale part 1 and a primary means 2 is inputted to a direction discriminating circuit 4 through an amplifying and waveform shaping circuit 3, is synchronized with a clock signal phi1 from a two phase clock oscillator 10, and an up or down count pulse is provided to an up-down counter 5. Its count data is inputted to a latching circuit 6 and is latched. This data is inputted to a microcomputer 7, also the microcomputer 7 sends a start signal to a synchronizing circuit 9, the circuit 9 is synchronized with a clock signal phi2, and a latch signal and a reset signal are sent to the latching circuit 6 and the counter. An operation result of the computer 7 is displayed on a display part 8. In this way, counting is executed exactly and also at a high speed without using an interruption processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10369380A JPS5729911A (en) | 1980-07-30 | 1980-07-30 | Counting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10369380A JPS5729911A (en) | 1980-07-30 | 1980-07-30 | Counting device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5729911A true JPS5729911A (en) | 1982-02-18 |
JPS636804B2 JPS636804B2 (en) | 1988-02-12 |
Family
ID=14360857
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10369380A Granted JPS5729911A (en) | 1980-07-30 | 1980-07-30 | Counting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5729911A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1982003682A1 (en) * | 1981-04-13 | 1982-10-28 | Sasaki Tsuneo | Displacement measuring device |
JPS59161915A (en) * | 1983-02-24 | 1984-09-12 | テキサス・インスツルメンツ・インコ−ポレイテツド | Synchronization decoding circuit |
-
1980
- 1980-07-30 JP JP10369380A patent/JPS5729911A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1982003682A1 (en) * | 1981-04-13 | 1982-10-28 | Sasaki Tsuneo | Displacement measuring device |
US4547667A (en) * | 1981-04-13 | 1985-10-15 | Tokyo Kogaku Kikai Kabushiki Kaisha | Displacement measuring device utilizing an incremental code |
JPS59161915A (en) * | 1983-02-24 | 1984-09-12 | テキサス・インスツルメンツ・インコ−ポレイテツド | Synchronization decoding circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS636804B2 (en) | 1988-02-12 |
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