JPS6367633A - Microprogram loading system - Google Patents

Abstract

PURPOSE:To omit an expensive boot ROM by using a clock generating circuit which can designate cycle based on a microprogram and a low-speed ROM. CONSTITUTION:The working is performed in a clock cycle suited to a low-speed ROM 4 when a power supply is applied and a microprogram loading job is carried out to a high-speed RAM 12 according to a microprogram stored in the ROM 4. When this loading job is through, the clock cycle is changed to that suited to the RAM 12 and the subsequent control jobs are carried out by the microprogram of the RAM 12. For this purpose, a clock generating circuit 5 is provided. The clock cycle of the circuit 5 is controlled by the microprogram stored in the ROM 4. Thus an expensive boot ROM can be omitted.

Description

[Detailed Description of the Invention] [Summary] In a microprogram-controlled computer system that uses a random access memory (RAM) as a control memory for storing microprograms, when the RA is turned on, etc.
In order to economically realize a microprogram loading means to the FI, the microprogram is equipped with a lock generation circuit whose cycle can be specified and a low-speed read-only memory (ROl'l). Sometimes, with a clock compatible with the above-mentioned low-speed R, high-speed I? is output from the ROM. A microprogram is coded in the AM, and after loading is completed, the microprogram loaded in the RAl'l is executed using a clock compatible with the high-speed RAM.

[Industrial application field]

The present invention relates to a microprogram loading method when power is turned on in a microprogram-controlled computer system.

Microprogram-controlled computer systems that require high-speed data processing require high-speed control storage devices.

In general, read-only memory (ROM) is suitable for storing high-speed microprograms, but it has the characteristic that when changes occur to the stored contents, they cannot be changed simply.

For this purpose, a method is used in which a high-speed random access memory (RAM) is used and a microprogram is loaded by some means, such as when the power is turned on.

In particular, recently there has been an increase in the number of highly integrated circuit devices (LSIs) that can incorporate random access memory (RAM). What is needed is a method for effectively loading microprograms into random access memory (RAM).

(Prior art and problems to be solved by the invention) FIG. 3 is a diagram explaining a conventional microprogram loading method, in which (a) shows a service processor (SVP)
(b) and (c) show a loading method using a bootstrap ROM (hereinafter referred to as BooFROM).

■ Loading method by the service processor (SVP): (a) See figure When the service processor (SVP) 2 reads the data to be coded (for example, a microprogram) from its own disk device 3 when the power is turned on, etc. This is a method in which the data is stored in the device 1.

In this method, service processor (SVP) 2
．． and a disk device 3 are required, and there is a problem that it is not economical unless it is a large-scale system.

■ Loading method using a boot ROM: (b) A boot ROM 13 is provided in the target device 1 to temporarily control the target device, and the boot ROM 11 of the target device 1 itself is the boot ROM 13. The bootstrap stored in
RAM) 12 and requires a disk device, so there is a problem that, for example, it is a loading method suitable for medium-sized systems, but not suitable for small-scale systems.

■ Loading method using high-speed boot ROM and low-speed large-capacity ROM: (C) See figure In this method, a large-capacity read-only memory (hereinafter referred to as ROM)4 is used as a file storage device. is used. At this time, RO1'l4 is rewritable, for example, and if it is implemented in a socket, the contents can be changed relatively easily.

As shown in this figure, when the power is turned on, the processor 11
Boo) Operates by ROM 13 and has a large capacity
A sequence is executed in which data (microprogram) is retrieved from ROM 4 and stored in random access memory (hereinafter referred to as RAM) 12. When the storage is completed, data processing is started by the microprogram in RAM IX. It is configured as follows.

In this case, since the operating speed of the processor 11 is fast, the Boo1-ROM13. A high-speed RAM is used for the RAM 12 and the RAM 12, but an economical RAM 4 has an access time that is an order of magnitude slower.

This method has the advantage that it is not necessary to use a disk drive as a file storage for storing the loading data. There was a problem that it was necessary to use , and it became a waste of time.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a microprogram loading method that does not require the use of an expensive Boolean FROM.

[Means for solving problems]

FIG. 1 is a principle block diagram of the microprogram loading method of the present invention.

In the present invention, a low-speed, large-capacity read-only memory (ROM) 4 is used.

a high-speed random access memory (RAM) 12; at least when power is turned on, microprogram data is stored from the low-speed read-only memory (ROM) 4 into the high-speed random access memory (RAM) 12; Random access memory (RAM) 12
In microprogram-controlled computer systems that are controlled by microprograms stored in
M) executing microprogram loading into the high speed random access memory (RAM) 12 by the microprogram stored on the low speed read-only memory (ROF 4), operating at a clock period adapted to the RAM 12; , When loading of the microprogram to the high-speed random access memory (RAM) 12 is completed, the clock cycle is changed to suit the high-speed random access memory (RAM) 12, and the clock cycle on the high-speed random access memory (RAM) 12 is changed. In order to execute subsequent control according to the microprogram, a clock generation circuit 5 whose clock cycle is controlled by a microprogram stored in the low-speed read-only memory (ROM) 4 is provided. .

[Effect]

That is, according to the present invention, in a microprogram-controlled computer system that uses a random access memory (RA4) as a control memory for storing microprograms,
In order to economically realize a means for loading a microprogram into the RAM at power-on, etc., a lock generation circuit is provided, in which a period can be specified by the microprogram;
By having a low-speed rewritable read-only memory (ROM), when the power is turned on, a microprogram can be loaded from the 8-bit ROM to the high-speed RAM using a computer compatible with the low-speed ROM, and the loading process can be performed. After completion, high-speed RA? Since the microprogram loaded in the RAM is executed using a clock compatible with
M is no longer required, saving mounting space and
When M is housed in a highly integrated circuit (LSI),
There is no need to worry about redesigning the highly integrated circuit (LSI) due to a program bug in the boot ROM.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which an external large-capacity W ROM 4. and if RO
The data transfer means from M4 to RAM 12 in the highly integrated circuit (LST) is the means necessary to implement the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

In this embodiment, the part within the dashed line indicates, for example, a highly integrated circuit (LSI), and to simplify the explanation, the instruction length is 16.
Assume that the target device 1 has fixed bits and a data length of 8 bits.

And RAM 12. It is assumed that the address for the ROM 4 is given by an 8-bit upper address (ZA) 15a and an 8-bit lower address (SA) 15b.

Further, the ROl'l 4 is, for example, a rewritable, large-capacity read-only memory (ROM), in which a microprogram used in the computer system is written by a writing means (not shown). A microinstruction read from such a 170M4 is O
It is latched into PRUG 14 and becomes an 8-bit instruction code and 8-bit data or address.

Now, when the power is turned on, flip-flop (FF) 1
The output of 6 becomes "0", and the multiplexer (MPX) 17c, R provided in the previous stage of OP REG 14
The clock generation circuit 5 supplies a clock suitable for the access speed of the ROM 4.

At this time, a predetermined address (
For example, set the RO address specified by that address.
Fetch the microinstruction from M4 and execute the above OP R
The instruction code is stored in the EG 14, the instruction code is analyzed, and a predetermined operation is performed.

The above R built in the device 1 is used as an instruction code.
A write command to AM 12 (e.g., WT RAMUP
PER instruction (write instruction to upper bit), WTRA
M LOWER command (old command to lower focus))
By preparing the command and setting the command for the capacity of the RAFI 12, the upper address (ZA) 15a and the lower address (S^) 15b can be sequentially incremented by a step circuit (not shown). As a result, the write instruction is read from the ROM 4, set in the OP REG 14, the instruction code is analyzed, and the 8 bits of the data section are sequentially stored in the upper and lower parts of the RAM 12. , the loading of the microprogram into the RAM 12 is completed.

After the loading of the microprogram is completed, the flip-flop (FF) 16 is set to 1 by the instruction read from the ROM 4, so that the multiplexer (MPX) 17 reads from the RAM.
12 side, the clock generation circuit 5 functions to supply a normal clock suitable for accessing the RAM 12 and thereafter executes the microprogram stored in the RAM 12. works.

In the above embodiment, the microprogram loading when the power is turned on is explained as an example, but the invention is not limited to this. For example, the loading of data by an instruction from an operation console, etc. not shown, etc. Needless to say, it can also be applied to

As described above, the present invention provides a rewritable, low-speed, large-capacity R in a microprogram-controlled computer system.
It is equipped with an OM and a high-speed RAFI, and when the power is turned on, the microprogram is loaded from the ROl'l to the RAM using a clock compatible with the ROFI, and when the microprogram loading is completed, the RAM is loaded. The feature is that the microprograms are sequentially read and executed from the RAM using a normal clock compatible with the RAM.

〔Effect of the invention〕

As described above in detail, the microprogram loading method of the present invention is applicable to a microprogram-controlled computer system that uses a random access memory (RAM) as a control memory for storing microprograms. In order to economically realize a means for loading a microprogram into a gate, a lock generation circuit whose period can be specified by the microprogram, and a low-speed rewritable read-only memory (RO
M), when the power is turned on, the low speed R
The microprogram is loaded from the ROM to the high-speed RAM using a clock compatible with the high-speed RAM, and after loading is completed, the above R is loaded with a clock compatible with the high-speed RAM.
Since it is designed to execute the microprogram loaded on the AM, an expensive boot ROF is required.
I is no longer required, saving mounting space and the boot RO
When M is housed in a highly integrated circuit (LSI),
There is an effect that there is no need to worry about redesigning the highly integrated circuit (LSI) due to a program bug in the boot ROM.

[Brief explanation of drawings]

FIG. 1 shows a basic block diagram of the microprogram loading method of the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a diagram explaining a conventional microprogram loading method. It is. In the drawing, 1 is the target device. 11 is a processor. 12 is random access memory (RAM). 13 is a bootstrap ROM or a boot ROM. 14 is OP REG, and 15a is upper address (ZA). 15b is a lower address (S8). 16 is a flip-flop (FF). 2 is a service processor (SVP). 3 is a disk device. 4 is a read-only memory (ROM); 5 is a clock generation circuit; are shown respectively. Unreleased Romon C My 20F Plus Gram Roping Method 2 Power R
Teribu'mouth/Tsuku Diagram 1 fig. wood flame θ month n-daishihi 1 Σ fig. 7" 1,
Figure 2 (C) X

Claims (1)

[Scope of Claims] A low-speed read-only memory (ROM) (4) and a high-speed random access memory (RAM) (12),
At least when the power is turned on, microprogram data is stored from the slow read-only memory (ROM) (4) to the high-speed random access memory (RAM) (12);
2) In a microprogram-controlled computer system that is controlled by a microprogram stored in
)(4), a microprogram stored on the slow read-only memory (ROM) (4) causes a microprogram to run on the high-speed random access memory (RAM) (12). After program loading is completed and loading of the microprogram into the high-speed random access memory (RAM) (12) is completed, the clock cycle is changed to suit the high-speed random access memory (RAM) (12), and the microprogram is loaded into the high-speed random access memory (RAM) (12). A microprogram loading method characterized in that subsequent control is executed by a microprogram on a random access memory (RAM) (12).