JPS6366657A - Microprocessor having capture mechanism - Google Patents

Abstract

PURPOSE:To improve the processing accuracy of a microprocessor having a capture mechanism by fetching the count data higher than an executing cycle from a time base counter when the edge of a capture signal arrives. CONSTITUTION:When the leading edge of an external signal arrives at an external signal input terminal 20, the count data is sent to a capture register block 700 from a time base counter 500. The result of this transfer is sent to an ALU 300, a register 100 or a RAM 200 via a capture controller 800 and a capture register block 700 by a specific instruction given from an instruction executing circuit 400. Thus the clock frequency of the counter 500 can be set at a high level regardless of the executing cycle of the circuit 400.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the configuration of a microprocessor, and in particular has a captain mechanism that can process external human signals that arrive asynchronously with the execution cycle of instructions of the processor with high precision. It provides a microprocessor.

BACKGROUND OF THE INVENTION In recent years, von Neumann microprocessors have been widely used in various fields, and they consist of memory means (generally called RAM) for temporarily storing data, and memory means for executing data operations. Arithmetic means (generally AL
It is called U. ), and an instruction execution means (generally composed of a program memory, an address counter, and an instruction decoder) that stores instructions to be executed sequentially and controls the operations of the memory means and the arithmetic means based on the instructions. It is characterized by being prepared. In addition, its typical configuration is
This is disclosed in Publication No. 3584 (hereinafter abbreviated as Document 1).

Problems to be Solved by the Invention By the way, the Neumann type microprocessor as shown in the above-mentioned document 1 processes data in a predetermined order, so it uses external signals that are input asynchronously. The problem is that the edge timing is slow to be captured. Conventionally, to solve such problems, a means called an interrupt or an input capture register mechanism has been used. However, the method using interrupt means has a problem of overhead (loss associated with the procedure before starting the interrupt handling routine), and although this overhead problem can be solved with the input capture register mechanism,
Since the operation of both is under the control of a timing generator that controls the instruction execution cycle, it is not possible to capture edge timing with a resolution higher than the instruction execution cycle.

By the way, such requirements, which can be said to be harsh on general-purpose microprocessors, often occur when microprocessors are used as controllers for precision machinery. ), if a microprocessor were to control the rotation, it would be necessary to capture the rotation detection signal with an accuracy within a few hundred nanoseconds in order to maintain high image quality, which would require the use of a special ultra-high-speed microprocessor. there were.

Means for Solving the Problems In order to solve the above-mentioned problems, a microprocessor having a capture mechanism according to the present invention includes a time base counter that counts a reference clock signal, and a time base counter that counts a reference clock signal and a time base counter that counts a reference clock signal when the edge of the capture signal arrives. It is provided with a capture circuit that captures count data whose minimum resolution accuracy is higher than the instruction execution cycle from the base counter and sends the result to the calculation means or memory means in accordance with a specific instruction from the instruction execution means.

Effect of the Invention With the above-described configuration, the present invention can provide a microprocessor that can process external input signals that arrive asynchronously with the execution cycle of instructions of the processor with high precision.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a microprocessor according to an embodiment of the present invention, and includes a register 100 for temporarily storing data and a random access memory (indicated by the abbreviation RAM in the figure). There are. Below,
It is abbreviated as RAM. ) 200, a 16-bit arithmetic unit (-indicated by the abbreviation ALU) 300 that executes arithmetic and logical operations on digital data, and a 16-bit arithmetic unit (-indicated by the abbreviation ALU) 300 that stores instructions to be executed sequentially and executes operations based on the instructions. and the register 100 and RA via the control bus 450.
M200, an instruction execution circuit (indicated by the abbreviation PLA in the figure) 400 that controls the operations of the ALU 300, and a 17-bit time base counter 500 that counts the reference clock signal applied to the clock terminal 10. The count data of the time base counter 500 is supplied via the counter bus 550, and the output data is sent to the register 100 and the RAM.
200, a data bus 60 connected to the ALU 300;
a capture register block 700 sent to 0;
External signal input terminal 20.30°40, 50.60.70
The capture controller 800 transfers the count data of the time base counter 500 to the capture register block 700 when an edge of six types of capture signals, each having a different generation source, arrives. Further, the reference clock signal applied to the clock terminal 10 is generated by a timing generator (indicated by the abbreviation TG in the figure) 90.
0 to the instruction execution circuit 400, and the data bus 600 includes a read-only memory (RON D).
1000. 110 Po) 1100. A-D converter 1
200. DA converters 1300 are connected, and further,
The RAM 200 and the ROMlooO each have an address decoder 250.1050.

Note that the capture controller 800 and the capture register block 700 take in count data from the time base counter 500 whose minimum resolution accuracy is higher than the instruction execution cycle when the edge of the capture signal arrives, and transfer the count data to the instruction execution circuit 400. A capture circuit is configured to send the result to the ALU 300, the register 100, or the RAM 200 according to a specific instruction from the ALU 300.

Regarding the microprocessor configured as above,
The operation will be explained with reference to the configuration diagram shown in FIG. 1 and the timing chart of the main parts shown in FIG.

First, FIG. 2A shows the clock signal waveform applied to the clock terminal 10 of FIG. 1, and FIGS.
, D, and E respectively indicate four-phase timing signals generated by the timing generator 500.
Reading out instructions from the instruction storage section of the instruction execution circuit 400 in synchronization with these signals, reading out data from each block including the RAM 200, and even reading out the A
The L U 300 executes calculations and transfers the calculation results to each block. Further, FIG. 2F shows a cycle of an instruction (one-cycle instruction) executed by the instruction execution circuit 400.

Next, FIG. 3 shows the capture controller 80 of FIG.
0 is a logic circuit diagram showing a specific configuration example of 0, and the external signal input terminals 20, 30, 40, 50, 60, 70 are equipped with control units 810, 820, 83 of the same configuration.
0, 840.850.860, and each of the control units 810 to 860 has a common reference clock input terminal 801 and a data transfer lock input terminal 802 to the capture register block 700, and further has an individual clock input terminal 802. It has reset signals 811-861, individual flag output terminals 812-862, and individual data transfer terminals 813-863. FIG. 4 is a timing chart for explaining the operation of the control unit 810 that constitutes the capture controller 800 shown in FIG.
FIG. 4B shows the clock signal waveform applied to the fourth clock.
This is a signal waveform obtained by frequency-dividing the signal waveform in Figure A, and this signal is used as a reference clock signal at the reference clock input terminal 8 in Figure 3.
01. Further, FIG. 4C shows a time base counter 5000 constituted by a synchronous counter that stops a master-slave type flip-flop in a unit stage.
This figure shows the count clock signal waveform of 1. The output of the master part of the flip-flop of each unit stage changes at the leading edge (the leading edge) marked with an arrow, and the output of the master part of the flip-flop of each unit stage changes at the trailing edge (the trailing edge). output changes. The fourth diagram shows a clock signal waveform for data transfer created from the signal waveforms of FIGS. 4A and B, and is supplied to the data transfer cock input terminal 802 of FIG.

Now, when the signal waveform shown in FIG. 4E is applied to the external signal input terminal 20 of FIG. 3, the level of the reference clock input terminal 801 becomes "
At the time when the output level of the NAND gate 814 shifts to "1" as shown in FIG. 4F, the level of the reference clock input terminal 8010 shifts to "O+".
At the time when the Q transition occurs, the output level of the NAND gate 815 transitions to "1" as shown in FIG.
1", the output level of the NAND gate 816 shifts to "B" as shown in FIG. 4H.
Each of the gates 814, 815, and 816 forms a bistable circuit with another NAND gate in pair, so when the output level shifts to "1", a reset signal is applied to the other NAND gate. However, when the output level of the NAND gate 816 shifts to "1", the paired NAND gate 81
7's output level transitions to "0'" and the AND gate 818
Since the output level of the NAND gates 814 and 815 also shifts to '0', the output levels of the NAND gates 814 and 815 return to '0'.

In this way, when the leading edge of the external signal arrives at the external signal input terminal 20, a signal waveform as shown in FIG. 4 is sent to the data transfer terminal 813 in FIG. 3 via the AND gate 819. This signal causes count data to be transferred from time base counter 500 to capture register block 700 in FIG.

The output signal of the NAND gate 816 is sent to the flag output terminal 812 and is used as a capture flag signal indicating that the time base counter 5000 count data has been transferred.
1, a reset signal is applied after software (program) confirms that this capture flag is set.

Next, FIG. 5 is a configuration diagram showing a specific example of the capture register block 700, in which data input terminals are connected to the DO terminal to D15 terminal, respectively, and data output terminals are connected to the D1 terminal to D16 terminal, respectively. Unit register 710.72 configured by 16 memory cells
0.730.740, and unit registers 750.760 constituted by 16 memory cells whose data input terminals and data output terminals are connected to terminals D1 to D16, respectively. Note that each unit register 710 to 760 has two control signal input terminals, one for reading terminals 711 to 761;
are each equipped with a capture controller 8 shown in Figure 3.
The data transfer signal from 00 is applied, and the select terminal 7
A select signal is applied to 12 to 762 for activating the output side of each unit register and reading it out to the data bus 600 in FIG. 1 via the data output terminals 00 to 015.

Now, in FIG. 5, the connection positions of the data input terminals and data output terminals of the unit registers 710 to 740 are shifted by one bit, but this is due to the following reason.

That is, the unit registers 750 to 760 are the same as the unit registers 750 to 760, and the LSB (i lower bit) of the time base counter 500 and the unit registers 710 to 740 are the same as the unit registers 750 to 760. The data input terminal is shifted to the left by one bit so that up to twice the number of bits can be processed at once.

With such a bit shift configuration of the unit registers 710 to 740, for example, when the Fl wavenumber of the reference value clock signal is selected to be 2 MHz, the unit registers 750 to 7
60 provides count data with a resolution of 500 nanoseconds, while unit registers 710-740
With this method, the arrival period of an external signal having a frequency of about 30 hertz can be measured in one process.

Effects of the Invention As is clear from the above description, the microprocessor having the capture mechanism of the present invention includes a time base counter 500 that counts the reference clock signal, and when an edge of the capture signal arrives, from the time base counter, The count data whose minimum decomposition accuracy is higher than the execution cycle of the instruction is taken in, and the result is calculated by a specific instruction from the instruction execution means (in the embodiment shown in FIG. 1, it is constituted by the instruction execution circuit 400). (In the embodiment, it is constituted by an ALU 300.) or memory means (In the embodiment, it is constituted by a register 100 or a RAM 200.)

) (In the embodiment, it is composed of a capture controller 800 and a capture register block 700). Since it can be set high without being constrained by the instruction execution cycle,
A microprocessor with high accuracy in processing external input signals that arrive asynchronously with the instruction execution cycle of the processor can be obtained, and a great effect can be achieved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a microprocessor in an embodiment of the present invention, FIG. 2 is a timing chart of the main parts of FIG. 1, and FIG. 3 is a specific logic circuit diagram of the capture controller 800 of FIG. 1. FIG. 4 is a timing chart for explaining the operation of the circuit shown in FIG. 3, and FIG. 5 is a configuration diagram of the capture register block 700. 100...Register, 200...RA
M, 300...ALU, 400...
- Instruction execution circuit, 500... Time counter, 700... Capture register block, 800... Capture controller.

Claims (2)

[Claims] (1) Memory means for temporarily storing data, arithmetic means for performing operations on data, and instructions to be executed sequentially are stored, and operations of the memory means and the arithmetic means are controlled based on the instructions. an instruction execution means; a time base counter that counts a reference clock signal; and a time base counter that captures count data having a minimum resolution accuracy higher than an instruction execution cycle from the time base counter when an edge of a capture signal arrives; A microprocessor having a capture mechanism comprising a capture circuit that sends a result to the arithmetic means or the memory means according to a specific instruction from the microprocessor. (2) A capture register to which the count data of the time base counter is supplied and whose output data is sent to a data bus connected to the arithmetic means; A microprocessor having a capture mechanism according to claim 1, wherein a capture circuit is configured by a capture controller that transfers data to the capture register.